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Old 2nd December 2012, 04:51 AM   #1591
ryanj is offline ryanj  Australia
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Default FIFO not locking - help please

Hi All,

I'm having an issue with the FIFO "locking".

I have TP48 connected to GND.

Im feeding the FIFO with I2S 16/44.1 from a QA550 SD card reader.

Whats strange is that it was working last night if i touched the Altera chip in the center of the plastic package...

Any advice anyone?

Thanks.
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Old 2nd December 2012, 05:52 AM   #1592
qusp is offline qusp  Australia
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wow Ryan, i'm a little stumped, ive fed fifo with all manner of sources, some great quality, some horrendus and i'm yet to find it doesnt lock.

have you tried another source? I suggest trying the spdif out of the QA550, using its i2s will not provide any benefit, or didnt you get the fifo spdif module? it could be some issue with the QA550 being battery powered, perhaps the i2s is offset and having issues? sorry ive not had to use TP48 being a test point, what is the purpose of that? to give it a ground??
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Old 2nd December 2012, 06:02 AM   #1593
ryanj is offline ryanj  Australia
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Thanks for the reply.

TP48 jumper connected to ground is to use "higher frequency XO (for example, use 22.5792 MHz XO for 44.1 KHz), or same XO frequency for two Fs (for example, use 22.5792 MHz XO for both 44.1 KHz and 88.2 KHz)."

I also bought the spdif module, but i'd need a better power supply to power that aswell.

So yes, im pretty stumped at the moment too.

The qa550 im using is running off a wall wart, not batteries.

Any other ideas? Anynody?
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Old 2nd December 2012, 07:59 AM   #1594
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Which clock module are you using Ryan? What is input fs and what clock speed are you using?

That jumper applies only to the single XO board as far as I can tell ...
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Old 2nd December 2012, 08:24 AM   #1595
ryanj is offline ryanj  Australia
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Yes, im using the single clock board. Input Fs is 256. MCLK is set at Fs 512. Master clock is at 22.5792 MHz.

Last edited by ryanj; 2nd December 2012 at 08:36 AM. Reason: Replied in the shed on my phone...
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Old 2nd December 2012, 12:47 PM   #1596
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Quote:
Originally Posted by ryanj View Post
Hi All,

I'm having an issue with the FIFO "locking".

I have TP48 connected to GND.

Im feeding the FIFO with I2S 16/44.1 from a QA550 SD card reader.

Whats strange is that it was working last night if i touched the Altera chip in the center of the plastic package...

Any advice anyone?

Thanks.
Hi ryanj,

Try spdif board or other i2s source to see if the problem still their.

Regards,

Ian
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Old 2nd December 2012, 11:32 PM   #1597
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Default Testing report of running ESS9018 with inverted MCLK

Running ESS9018 with inverted MCLK is an interesting topic. Somebody thinks its important, while others seems dont much care about it. So, I did some real test on this issue with Si570 clock board V2.0 and my BIII DAC today.

Si570 prototype clock board V2.0 was configured into both normal and inverted MCLK mode. Please see the screen shoot pictures below of the waveform testing result. The white waveform is the ESS9018 MCLK running at 98.xxx MHz, the green waveform is the eye of I2S BCK (or SCK, WS and SD as well) signal. We can see, with normal phase MCLK configuration, changing on I2S signals follows the raising edge of MCLK. While with inverted MCLK configuration, changing on I2S signals follows the falling edge of MCLK. With the Potato 74G74 being as the re-clock FF, the delay Tpd is around 2ns and the raising/falling time is around 0.6-0.7ns. Si570 clock board was powered by an external TPS7A4700 reg PCB with a battery pack as the DC input.

The interesting thing is they really sound a bit different. But Im not quite sure which one is better. The normal phase MCLK already sounds very good, when it turns to the inverted MCLK, feels the background a bit more quiet and dark. Its more obvious running at 45.xxx/49.xxx MHz then at 90.xxx/98.xxx MHz. Maybe I already got familiar with the sound of normal MCLK, feels wise, the normal MCLK sounds a little bit rich. But, overall, I still think the inversed MCLK plays positive.

Based on my testing result, I think I have to include this normal/inverted MCLK feature into Si570 clock board V3.0 design. But my question is which one is better to be as the default configuration?

Ian
Attached Images
File Type: png NormalMCLKG74.png (40.9 KB, 274 views)
File Type: png InvertedMCLKG74.png (41.8 KB, 239 views)
File Type: jpg Si570Board.JPG (200.9 KB, 251 views)
File Type: jpg system.JPG (157.4 KB, 242 views)
File Type: jpg TPS7A47RegMLCC.JPG (107.6 KB, 236 views)
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Old 3rd December 2012, 12:15 AM   #1598
ryanj is offline ryanj  Australia
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Quote:
Originally Posted by iancanada View Post
Hi ryanj,

Try spdif board or other i2s source to see if the problem still their.

Regards,

Ian
Hi Ian, i tried another source, same problem.

Although if you give the Altera chip a tickle on the right side halfway up; it starts locking with the "lock" and "empty" leds flashing...

Could it be a dry solder joint?

On close inspection of the Altera chip i noticed a very small amount of solder half way up one of the legs nearly touching the leg next to it, this is the same place described above. Solder was removed, but the problem remained.

Sorry for my ignorance, this project may just defeat me! So very close though, its playing me sweet music right now.. just had to tickle it... i know its weird.
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Old 3rd December 2012, 01:37 AM   #1599
AR2 is offline AR2  United States
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Quote:
Originally Posted by ryanj View Post
Hi Ian, i tried another source, same problem.

Although if you give the Altera chip a tickle on the right side halfway up; it starts locking with the "lock" and "empty" leds flashing...

Could it be a dry solder joint?

On close inspection of the Altera chip i noticed a very small amount of solder half way up one of the legs nearly touching the leg next to it, this is the same place described above. Solder was removed, but the problem remained.

Sorry for my ignorance, this project may just defeat me! So very close though, its playing me sweet music right now.. just had to tickle it... i know its weird.
You could try to reflow all the connections on the chip. You could do it carefully by touching every leg. It might help if you add tiny amount of solder why you doing it. Check any other connections as well, because it might happen that while you are rocking chip, some other connection is acting, and it falsely appears as if the chip is at fault. Maybe wires to and from board?
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Last edited by AR2; 3rd December 2012 at 01:43 AM.
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Old 3rd December 2012, 01:43 AM   #1600
ryanj is offline ryanj  Australia
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Hi AR2,

Thanks for your input, but i re flowed last night with no change unfortunately. I'll have another look at other areas that may be loose.

Cheers

Last edited by ryanj; 3rd December 2012 at 01:45 AM.
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