Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[454Casull]

Originally Posted by iancanada

Impedance matching is very important for all high frequency RF signal transmission as well as clock signal. It's not for video 'only' . Actually S/PDIF signal is not a audio signal. It's kind of bi-phase mark code and should be look upon as a clock signal. If we don't have good impedance matching, the reflecting signal will be added over the clock and introducing more jitter. Ian

What you say may be quite true - I was thinking of an analog signal...

[qusp]

Erno Borbely famously terminated all his BNC analogue transmission lines as well.

very nice quality boards, keep me in mind for a set when you look to doing a run. or at least le me know the wallet damage and i'll let you know. if its not under NDA i would have no problems soldering my own boards

[Kurt von Kubik]

Nice thread
A lot to read and a lot to learn
Keep it up guys.

Btw. reading your discussions I ran into a few things, that might to both you guys and me.

The WM8741 chip from Wolfson is described sounding "not clear"
To that I can say that it actually is like that. Both the 8740 and 8741 which i happened to listen to, are pretty dull and lazy to listen to.
I also think that characterizing that as analog sound is wrong. Good analog sound is much more lifelike than this. And actually it is quita a riddle to me how Wolson managed to get reasonably precise digital recordings to sound like this.
In need of an U out chip I would go for CS or AK instead.

About the whole idea with a FIFO of a certain size to minimize jitter, has always been one of my favourite thoughts about digital audio.
But is there any particular reason why you do not talk about up-sampling?
Up-sampling is as far as I know, seen as a very effective way of managing jitter already present in the signal.
Of course it would be even better if it was not there at all, but still it seems very attractive.

[TheShaman]

Very interesting project, Ian.
I second qusp's recommendation for a GB!

Originally Posted by iancanada

Working with the FIFO board and clock board, 3 hours bit perfect loop test was passed with up to 192Khz/24 bit setup and for both coaxial and optical connection;

So, Toslink 24/192 is actually feasible using standard Toshiba TORX147/TOTX147 parts? I thought the bandwidth of these parts was not enough and, sadly, the 25Mbps parts (TORX142/TOTX142) have been discontinued.

[Turbon]

I would also like to see a GB on this.

Brgds

[GOR3]

Ian,
I think you tried the Crystek CCHD-957. What were your impressions?
BR,
George

[jcarr]

At least in Japan, it appears that if you contact an official Toshiba distributor and make a custom purchase order for TOSLINK components that are rated for 192kb operation, it is still possible to order and purchase such components from Toshiba.

Do expect to pay for whatever minimum quantities are required.

hth, jonathan carr

[qusp]

are C4 and C9 some sort of capacitor network? they appear to have 4 terminations

[iancanada]

Originally Posted by qusp

Erno Borbely famously terminated all his BNC analogue transmission lines as well.

very nice quality boards, keep me in mind for a set when you look to doing a run. or at least le me know the wallet damage and i'll let you know. if its not under NDA i would have no problems soldering my own boards

Hi qusp,

Thanks again for the recommendation of the U.FL connectors. I'm very happy with them. It get the signal improved obviously. I use both U.FL conncetors and cables in almost all of my projects now.

Very glad you want the KIT. Once I go through the fully test on all the second edition PCBs and make sure everything is OK with bug free, I will consider setting up a group buy. I could figure out how much work I have to do going a small quantity production. Don't warry about your wallet, I'll give you a surprise .

[iancanada]

Originally Posted by simmconn

Nice looking board!

Wait... Why would you use a TX since the S/PDIF format is inherent prone to jitter? Shouldn't the output of the FIFO go directly to the DAC?

You know you could implement both S/PDIF RX and TX in the PLD with many benefits.

Thanks simmconn,

The S/PDIF interface board is a very flexible design. Basically, on board, it has a DIR and a DIT which are independent from each other. You can use it as a S/PDIF receiver and feed the I2S signal directly to the DAC form the clock board, which might the way you want; or,you can loop the I2S to the S/PDIF board and make it working as a S/PDIF FIFO; and or, your can make it doing both at same time.

Including the S/PDIF receiver and transmitter into FPGA design is a smrt idea. But my considerations in this project are:

1. Actually I can do this, but the problem is I need more logic cells and other resourses. That means I have to use larger CPLD/FPGA than the CPLD I'm useing now. The DIX9211 is just an $5 chip,the cost would be less then enlarging the CPLD/FPGA;

2. My design idea is kind of open concept. I need to keep the S/PDIF board independent from the FIFO and clock board, in case somebody else want to use their own S/PDIF interface solution, or just don't use it at all;

3. Use a commercial IC like DIX9211 is safer for this project, at least it guaranteed fully tested by the group from TI/BB.

Ian