Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 157 - diyAudio
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Old 24th November 2012, 02:27 PM   #1561
qusp is offline qusp  Australia
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i2s fifo buffer (finished and available)
spdif board (finished and available)
dual clock board (finished and available)
battery management board (finished and available)
isolator board (next GB I think)
Si570 multi frequency Clock board (nearing end of development, ready for next GB I think)
PCM daughterboard and level-shifter for NOS dacs (nearing end of development, but not yet available)
u.fl adapters (available)
Clock adapters (available)
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Old 25th November 2012, 12:20 AM   #1562
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Si570 interest list:

1. bigpandahk
2. tagheuer
3. hochopeper
4. qusp (of course)
5. AR2 - definitely!
6. wktk_smile
7. hirez69
8. CeeVee - you bet!
9. number9
10. analog_sa - GB maniac
11. edbk
12. atom6422
13. misterrogers X2 - Of Course!
14. NicMac - as usual!
15. Zoran
16. PET-240
17. Coolhead
18. Slartibartfasst
19. SYklab
20. Regland
21. Neb001
22. SPWONG
23. Greg Stewart (also of course!)
24. Vitalica
25. spm
26. Fridrik
27. ccliu
28. makumba1966
29. lindamar
30. Finaxe
31. Odysseas x2
32. palmito
33. crazikid
34. deanoUK
35. Julf
36. DUC985
37. rsotirov
38. kvl
39. bkdog
40. necplusultra
41. Nikola Krivorov X2
42. nvduybom
43. Popolvar
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Old 25th November 2012, 07:44 PM   #1563
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Default Low noise\ripple supply

Hi, Just to say your are no fun guys ;-). you are working to fast and specialy Ian
Preparing for the arrival of my Fifo I was shopping for a nice LDO regulator to replace a LM7805 and a LM2937ET-3.3 on my DUAL Mono PCM1794A DAC board. Browsing on the TI site I saw the TPS7A4700 LDO what a nice chip: good specs (1A), simple design but wait I saw it somewhere before .... hum Oh no not in the fifo thread ;-)

Ian any chances your include the TPS7A4700 PCB in GB4 ?

So back in lazy mode for now ;-)

Last edited by Fridrik; 25th November 2012 at 07:49 PM.
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Old 26th November 2012, 03:01 AM   #1564
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Quote:
Originally Posted by Fridrik View Post
Hi, Just to say your are no fun guys ;-). you are working to fast and specialy Ian
Preparing for the arrival of my Fifo I was shopping for a nice LDO regulator to replace a LM7805 and a LM2937ET-3.3 on my DUAL Mono PCM1794A DAC board. Browsing on the TI site I saw the TPS7A4700 LDO what a nice chip: good specs (1A), simple design but wait I saw it somewhere before .... hum Oh no not in the fifo thread ;-)

Ian any chances your include the TPS7A4700 PCB in GB4 ?

So back in lazy mode for now ;-)


TPS7A4700 reg board is under evaluation now. I'll include it in GBIV if I'm satisfactory with it.

Thanks,

Ian
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Old 26th November 2012, 03:27 AM   #1565
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Default Inversed MCLK for ESS9018 in asynchronous mode

glt mentioned that inversed mclk would be better for ESS8018 running at sync mode. I read the ESS application note, it really make sense.

I think we need include this feature into the Si570 clock board Ver3.0.

Here I attached the waveform of I2S with normal MCLK and inversed MCLK. The difference on timing in between is very clear. I’ll do some real measurement on this issue later on.

Ian
Attached Images
File Type: png NormalMCLK.png (16.8 KB, 371 views)
File Type: png InversedsedMCLK.png (17.1 KB, 369 views)
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Old 26th November 2012, 03:41 PM   #1566
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Hi Ian,

Although I may be wrongly getting the credit for "mentioning it", I don't understand what you are implying regarding the timing "making sense". could you explain?

And thanks for moving the state of the art forward and benefiting us in the process...
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Old 26th November 2012, 09:55 PM   #1567
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Quote:
Originally Posted by glt View Post
According to this app note: http://esstech.com/PDF/Application_N...PCB_Layout.pdf on page 5:

"If operating with a synchronous MCLK, it is recommended to use an inverted MCLK. The inverted synchronous MCLK ensures that the Sabre noise is as low as possible."
Quote:
Originally Posted by glt View Post
Hi Ian,

Although I may be wrongly getting the credit for "mentioning it", I don't understand what you are implying regarding the timing "making sense". could you explain?

And thanks for moving the state of the art forward and benefiting us in the process...
Thanks glt for the good suggestion. This issue might be connected to ESS9018 internal ASRC architecture and timing. As ESS application note recommended a inverted MCLK to ensure a lower noise at sync mode, I think 9018 was optimized to the inverted MCLK. I'll give a try on Si570 clock board.

Ian
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Old 26th November 2012, 10:06 PM   #1568
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Quote:
Originally Posted by glt View Post
Hi Ian,

Although I may be wrongly getting the credit for "mentioning it", I don't understand what you are implying regarding the timing "making sense". could you explain?

And thanks for moving the state of the art forward and benefiting us in the process...
I know nothing about inside of ESS dac. But from the timing, You can see with the inverted MCLK, the changing on I2S signal has more delay from the raising edge of MCLK than the normal one. I guess this may give ESS9018 a bit more "clean time" before issue a DS pulse. But I might be wrong .

Ian
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Old 26th November 2012, 10:15 PM   #1569
qusp is offline qusp  Australia
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yeah ha look I dunno, I know I asked for it ages ago by email or one of the threads (in May'ish), probably lost in the noise, but I was only parroting it from the datasheet and the Japanese crew so honestly its not really something I should get credit for either. Acko is playing with it also afaik and I have that option on titan, which was also initially designed for an ESS

Last edited by qusp; 26th November 2012 at 10:31 PM.
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Old 26th November 2012, 10:17 PM   #1570
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Quote:
Originally Posted by iancanada View Post
I know nothing about inside of ESS dac. But from the timing, You can see with the inverted MCLK, the changing on I2S signal has more delay from the raising edge of MCLK than the normal one. I guess this may give ESS9018 a bit more "clean time" before issue a DS pulse. But I might be wrong .

Ian
Now that is an interesting concept Ian. Is the transition from high->low 'softer' also?
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