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Old 31st October 2012, 06:39 AM   #1371
qusp is offline qusp  Australia
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the spdif board has u.fl, but they are just optional connectors to connect to the fifo board, which again has optional u.fl to connect to the clock board. none of that has any impact on your connection to the ackodac so you can just leave them as u.fl, or as I do, just use the ribbon connectors to interconnect the boards, the only important connection is that to the dac and all of the dac connections for i2s are from the clock board, which I have changed to w.fl, but left the MCLK as u.fl to match the dac. I dont find them any more fiddly than u.fl
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Old 31st October 2012, 08:25 AM   #1372
qusp is offline qusp  Australia
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my post in reply to this was deleted by EXADEVICES, so perhaps it should be corrected here where he has no moderation power.

it was predictable that he would rather leave the incorrect marketing information stand while editing replies.unfortunately I thought I had saved it, but I sent hochopeper a link instead and wayback doesnt have it
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Old 31st October 2012, 08:42 AM   #1373
NicMac is offline NicMac  Italy
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Yes - exa65 tells stories and delete whatever he dislikes.
Not strange as he clearly have strong competition and not strange that his clients supports him as they already spend the money........
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Old 31st October 2012, 09:43 AM   #1374
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Quote:
Originally Posted by qusp View Post
the spdif board has u.fl, but they are just optional connectors to connect to the fifo board, which again has optional u.fl to connect to the clock board. none of that has any impact on your connection to the ackodac so you can just leave them as u.fl, or as I do, just use the ribbon connectors to interconnect the boards, the only important connection is that to the dac and all of the dac connections for i2s are from the clock board, which I have changed to w.fl, but left the MCLK as u.fl to match the dac. I dont find them any more fiddly than u.fl
I was thinking about this today. It may be of value, when we move to even higher frequencies being transmitted over the cables (ie Si570 @ frequency approaching 100MHz) to use u.fl between fifo/isol/clock board. As frequencies increase the loop areas decrease and the smaller gaps between wires in ribbon/fpc cable, that were previously ok, might no longer act as we desire. While the i2s signal integrity may be ok and cleaned up by the reclocking board. We may be creating additional noise emissions within the DAC enclosures as a side-effect of pushing for ever faster frequencies. Just a thought.

My idea above is basically my thoughts following reading this article:

http://www.hottconsultants.com/pdf_files/dipoles-1.pdf

and particularly this excerpt from the last page of that article as I quoted on another thread earlier today:

Quote:
Last, but not least, we could shield the cable and terminate the shield properly (360 degree connection) to the chassis. In this case the cable effectively does not leave the enclosure. You can think of the cable shield as just an extension of the chassis, and how well it does or doesn’t behave in this manner is a strong function of the shield to chassis connection.
My basic understanding of what I've read from other 'tech tips' on the Hott website is that separation of gnd/signal wires should not be more than 1/20th of the freq being transmitted. In our case we have to consider the harmonics generated in the creation the clock waveform, which will be dependant on the slew rate of the square wave. Anyone have any ideas on this effect and its relevance?
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Old 31st October 2012, 10:20 AM   #1375
marce is offline marce  United Kingdom
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The GND (return path) should be adjacent to the signal, when you start getting into 100MHz signals, you can easily inroduce signal integrity problems. The main concern is avoiding impedance mismatches as you go from on board to another, and distance is also critical, they dont like going a long way, depending on the driver, receiver and cable used for transmission.
Samtecs range of high speed cables to give you an idea of what is used for high speed signal transmission:
Samtec | High Speed Cable Assemblies
Another methos widely used is either FPC/FFC connectors and cables or bespoke two plus layer flex caqbles with a ground plane and the respective connectors. Preferably the signal should travel over a contigous return plane (GND) from transmittor to receiver, or if only one or two signals then co-ax cable with rf connectors.
The frequencies that are of concern are determined by the knee frequecy:
Fknee=1/2tr where tr is the 10-90% rise time of the signal.
This is also the determining factor on whether a design is high speed, not the ultimate clock frequency.

The following links are some of the main people for signal integrity:

beTheSignal.com
Signal Consulting, Inc. - Dr. Howard Johnson
Speeding Edge consultants specialize in high-speed PCB and system design disciplines
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Old 31st October 2012, 12:03 PM   #1376
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Thanks marce!

I have more reading to do


To be clear, my post above I was mostly thinking about the JST PH series 2.0mm pich wires that are available on the FIFO and suggesting that with the faster clocks we might be getting past their useful frequency range for i2s signals. Now I need to go and learn more about rise time, now that you mention it in that way and make me think about it again, it does seem logical that the harmonics that make up the analogue signal are related to how tight the square is on the signal and hence the rise time becomes the critical factor.
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Old 31st October 2012, 12:11 PM   #1377
qusp is offline qusp  Australia
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Thanks marce, its already tested bitperfect in loop testing at these higher frequencies, so thats no worries. As hochopeper says the concern if any will be the radiated noise. actually its possible Ian is already using the optional u.fl for these intermediate ICs, easy fix to just use them as they are already there, the other cable is FPC.

yeah I looked into getting a custom flex cable/PCB done up for my portable dac, too pricey for one off designs still at this stage.

regardless AR2, you dont need to deal with w.fl on these interconnections from spdif->fifo board->clock board, worst case would be having to use the u.fl positions instead of the ribbon; you only need the w.fl + u.fl on the i2s output from the clock board

Last edited by qusp; 31st October 2012 at 12:14 PM.
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Old 31st October 2012, 01:45 PM   #1378
qusp is offline qusp  Australia
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Quote:
Originally Posted by hochopeper View Post
Thanks marce!

I have more reading to do


To be clear, my post above I was mostly thinking about the JST PH series 2.0mm pich wires that are available on the FIFO and suggesting that with the faster clocks we might be getting past their useful frequency range for i2s signals. Now I need to go and learn more about rise time, now that you mention it in that way and make me think about it again, it does seem logical that the harmonics that make up the analogue signal are related to how tight the square is on the signal and hence the rise time becomes the critical factor.
yeah I guess youve missed marce's posts on this before, I was intrigued to know thats what they are referring to when they say high speed layout, the rise time/slew, not necessarily the frequency
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Old 31st October 2012, 01:58 PM   #1379
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Quote:
Originally Posted by qusp View Post
yeah I guess youve missed marce's posts on this before, I was intrigued to know thats what they are referring to when they say high speed layout, the rise time/slew, not necessarily the frequency
I think I had seen them but, at the time, not fully comprehended. I previously had an overly simplistic mental picture, basically I had not considered that the rise time as a proportion of the signal period could be varied to improve the signal transmission. I had fallen into what I suppose is a someone 'rookie mistake', of thinking 'the squarer is better'. Which, with a different perspective, is obviously not the case for either integrity of the signal or the radiated noise. Now I realise I was to an extent pursuing the right solutions for the wrong reasons.

I still think its a fair call to reconsider some of the transmission medium we use between these boards as we move to faster clock frequencies, especially with consideration for radiated noise, considering that we are now up to 4x the clock speed the design started with. I am not sure how much this has changed the rise time but I am guessing there has been some change in that regard also?

Last edited by hochopeper; 31st October 2012 at 02:03 PM.
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Old 31st October 2012, 03:12 PM   #1380
qusp is offline qusp  Australia
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think of it the same way you would sharp edges on a baffle, at the sharp edges you get a more destructive diffraction of the sound wave that sprays harmonics out from the corner. that edge is where the change in current/transient occurs and a square will obviously be a more accelerated change than a sine for the same total energy

I guess thats also what resistive termination is about. but a balance has to be struck, we are not dealing with a digital end result, clock is very much an analogue signal, similar to more RF than digital. The edge does need to be maintained, we dont just need an accurate decision point, its somewhat more stochastic than that IMO. We cannot damp the edge too much as we are without any form of error correction, well not at the clock board anyway, we just need to be aware of the facts and minimize the negative side effects

maybe this is a good reason to use sine wave clocks?

nah I dont think anything needs reconsidering at all, there are 2 options, one has always been the easy/cheap way out, the other is good up to 6GHz. the other parts on this design have been designed for much higher speeds than the audio data from the beginning, the clock is still a long way from encroaching on that. the Si570 board will have been designed for higher speeds from the outset and all lines are terminated.

Ians background is in high speed digital medical instrumentation, pretty sure the speeds hes used to dealing with for ADCs and sensors in that area are going to be running higher speeds than here. one thing that will definitely need to be considered is how the battery packs are hooked up, most batteries are natural and inductive dipoles

Last edited by qusp; 31st October 2012 at 03:14 PM.
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