Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

Hi guys,

I'm just trying to figure out what to use to power my fifo-isolator-si570 combo, and I definitely could use some advice from the experts here.

I’m using TPA Placids in my build, and the one powering the BIIIES heats up to 60-64 C drawing 460 mA, so I’m a little concerned about the heat that another shunted reg would produce with around 650 mA (according to Ian’s docs, that’s what the fifo and the Si570 need). Besides, I’m not sure if a placid can go up to 650 mA, probably not without any mods (bigger heatsinks for sure).

Do you guys think that a sigma11 could be a suitable option?

I’ve been looking trough the thread and seems like some of you are using Salas shunted reg and others are using batteries. Well… here’s where I have to confess my complete ignorance…:eek: can anyone help me a little bit with the passive battery management board? I would really appreciate if someone could point me to an appropriate set of batteries (LiFePo4 maybe?) and a suitable battery charger. What do you use as control voltage? (the fifo's 5V output?)

Many thanks for your help! :)

There has been some recent discussion on the load of the FIFO boards with a break down in this post - http://www.diyaudio.com/forums/digi...mate-weapon-fight-jitter-248.html#post3383928

Ian has said he suspects the FIFO measurement in that post is a bit under-done, suggesting that perhaps closer to 80mA is a better value, see here -
http://www.diyaudio.com/forums/digi...mate-weapon-fight-jitter-249.html#post3385860

Are you not using the isolator between the FIFO and the Si570? I personally don't agree with the common misconception of audiophiles to put shunts everywhere. For example, a shunt in this location as a pre-regulator has little benefit as the load the pre-reg sees is only the local regulator and it's associated capacitors. I will be using LT1963 and LT1085 for my pre-regulators. I suspect that there are other things changing that result in the subjective observed improvement when people change to pre-regulators that results in their preference for these. We've had that debate in this thread before IIRC and I have no desire to re-visit that again though I feel like I should mention it since you're struggling with the heat dissipation of the shunts perhaps unnecessarily.


If you follow those links I hope you'll find some of the answers to your questions and people can answer more specifically if you give a few more details on how you're configuring your system.


Cheers,
Chris
 
Hi guys,

I'm just trying to figure out what to use to power my fifo-isolator-si570 combo, and I definitely could use some advice from the experts here.

I’m using TPA Placids in my build, and the one powering the BIIIES heats up to 60-64 C drawing 460 mA, so I’m a little concerned about the heat that another shunted reg would produce with around 650 mA (according to Ian’s docs, that’s what the fifo and the Si570 need).
Many thanks for your help! :)

Powering Fifo and si570 from the same PSU is not recommended, especially when
using isolator.

So you need 2 "smaller" power supplies, not ONE ~650ma power supply.
 
Hi guys,

Thanks all for your replies, really appreciated. I’m afraid I jumped too late into this thread (and into this forum also) and I’m a bit lost with all the information available.

Thanks hochopeper for pointing me to those posts (also, thanks for the wiki, it’s being really helpful). I’ve tried to skim trough the whole thread to find all the useful information, but I missed that, sorry. Now, 80mA for the FIFO seems to be more reasonable than 500mA considering that the FPGA (I’m assuming that it’s the most power demanding device of the board) needs a peak of 55 mA on startup and an average of 12mA (maybe 500 mA is for FIFO+dual clock?).

Anyway… guys, I’ve just re-read what I posted and I’m sorry. Oh my god it’s wrong in almost every way. I could blame my poor English or the lack of sleep because of having a baby or the lack of time because my job getting into my spare time, but no excuses.

Please, let me try again… I’m building a TPA BIIISE with an IVY III as the output stage. Right now I’m powering the IVY III with a Placid HD BP and the BIIISE with a Placid HD. I’m also using Amanero as USB input, right now USB powered.
What I intend to do is to add the FIFO + isolator + Si570 (with TPS7A regulator) in between the Amanero and the BIIISE.
My concern was that, if I use another shunted reg (another Placid or a Salas shunt) for powering the Si570 board, and the Placid HD to power both the BIIISE and the FIFO, I would have to deal with extra heat. Seems like this won’t be too difficult if the FIFO draws around 80mA – 100 mA. Also, I was wondering if it’s necessary to go shunted for everything as the FIFO is basically just an FPGA with its own on-chip voltage regulator and I will be using TPS7A regulator on the Si570.

And the question that I really wanted to post is: do you guys think that, using one sigma11 for powering the FIFO (maybe other future elements of the build also) and another sigma11 for powering the Si570 is a good option?

And… the answer that I gave to myself this morning (after 6 hours of sleep, thanks god) is: go and find it by yourself!!! :).

Regardind the batteries... I ordered one battery management board, but just because I didn't want to regret later. The only experience I have with batteries is replacing the ones of the TV remote. As a completely ignorant in batteries I'm afraid of doing something stupid with them and setting the house on fire. Maybe for the next build...

Sorry for all this noise.
 
I have a few questions I hope someone can answer :)

I'm using a wavio for input (44-192 samplingrates) and the spdif board as output.

1) Im now using the dual XO board with the 22/24M clocks, can I switch to using the sis clockboard? If yes what is the maximum clock rate the spdif board can handle? 45/49M for 176/192K? Or is my dac the rate limiting device.
2) Does it make sense to use the isolator board when using the spdif board since it is powered from the fifo board?
3) If I power the spdif board seperately can I remove the ribbon cable between fifo and spdif board?

Many thanks in advance :)

An externally hosted image should be here but it was not working when we last tested it.
 
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I need help.
I want to use this Renderer which has clock 22/24, I2S output and input external clock. Media renderer | ABC PCB
What is correct in synchronously:
- To go the external clock Si570 in Renderer and BuffaloIII?
- To go the external clock Si570 only Buffalo III?

Thank you!
 

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I have a few questions I hope someone can answer :)

I'm using a wavio for input (44-192 samplingrates) and the spdif board as output.

1) Im now using the dual XO board with the 22/24M clocks, can I switch to using the sis clockboard? If yes what is the maximum clock rate the spdif board can handle? 45/49M for 176/192K? Or is my dac the rate limiting device.

clocks on dual XO board can be safely replaced with 45/49M ones, as described
in the manual.

Required MCLK(on dual xo board) frequencies for 176k/192k playback varies depends on the Dac and configulation you use.
 
I need help.
I want to use this Renderer which has clock 22/24, I2S output and input external clock.

What is correct in synchronously:
- To go the external clock Si570 in Renderer and BuffaloIII?
- To go the external clock Si570 only Buffalo III?

Thank you!

Use MCLK output of the si570 board as a MCLK of the BIII, then BIII will receive
syncronously running i2s and 90/98M master clock (Make sure Crystek 100M master clock on BIII disabled).

I'm not familiar with the Media Renderer, so I don't know there's any benefit in
feeding BIII and Renderer at the same time from si570.
 
clocks on dual XO board can be safely replaced with 45/49M ones, as described
in the manual.

Wouldn't you have to make sure that all your SPDIF DITs and DIRs are...comfortable with those higher clock speeds?

Quoting the dual-xo board "double-speed" manual:
Dual XO Clock Board has a reserved double speed mode which could allow XO frequency going up to 45.1584 MHz and 49.1520 MHz to meet this kind of requirements. The double speed mode is not recommended to classical DACs and S/PDIF DITs to avoid any risk of possible damage.

I suppose the recommendation stands for clocks which natively run at said frequencies as well.
The DIX9211 on the SPDIF board should be OK (it's listed as 55.296MHz max on the datasheet), but I'm not sure about other transceivers.
 
From the Si570 manual:

The Si570 Clock Board operates in the double speed mode natively. It is not recommended to feed its MCLK into the DIT section of the S/PDIF board as part of a S/PDIF FIFO (can work with S/PDIF DIR without problem). If necessary, the MCLK from the FIFO board may be fed to the S/PDIF Interface board MCLK U.FL socket.

When avoiding 352/384k sampling rates the clocks should run at 45/49M max according to the manual for all groups. So could I use the si570 with spdif board then?

Thanks :)
 
are you hoping to output spdif, or input spdif?

these comments relate only to outputting spdif, when inputting (which will only allow max 192 or maybe 216khz input) the fifo will select the correct clock speed on the si570 based on the incoming sample-rate
 
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Output to a consumer dac (lavry) with ad1896 src and ad1955 da, the ad1896 downsamples 176/192 to 96 (dunno why). 1896 datasheet says max masterclock 30 MHz, but cant really discern what the max input rate would be. Anyway i'm a n00b clearly :eek:

I understand it would be easier to just buy 2 crystek clocks and use the dual xo board but I plan to buy a new dac as soon as funds permit and already have the si570 board so would rather use that :)
 

TNT

Member
Joined 2003
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Hello Ian,

did you see any chance to save the status of the input selector?
The standard starting with the optical input is suboptimal for everyone, who use another input like the backdoor I2S.


Best regards,
Oliver

:wave:


When timing is fixed downstream, opto is not a bad option as it gives galvanic separation. Do you suspect data loss?

Or are you playing a lot of hires making toslink impossible?

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