Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 124 - diyAudio
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Old 19th October 2012, 11:55 AM   #1231
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Old 19th October 2012, 01:26 PM   #1232
syklab is offline syklab  Hong Kong
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Old 19th October 2012, 03:03 PM   #1233
Regland is offline Regland  Canada
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Old 19th October 2012, 03:09 PM   #1234
glt is offline glt  United States
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Quote:
Originally Posted by analog_sa View Post
Finally put together a test bed: a modified exaU2I via I2S FIFO to Buf 3. As the EXA already has a FIFO and i feed its onboard clocks from a separate regulator, it is not a likely candidate to benefit from the FIFO board.

...
Could you show a picture of your FIFO implementation?
Thanks.
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Old 19th October 2012, 03:17 PM   #1235
qusp is offline qusp  Australia
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I would be very surprised if EXA approached the levels of jitter possible with fifo, the clocks do not directly feed the output MCLK with EXA afaik, at least last time I looked (some time ago now) it didnt

confirmed, it still doesnt, the clock clocks the FPGA, which outputs the i2s through the GMRs, so thats 2 layers of additive jitter after the clock, pretty different situation to what we have here

Last edited by qusp; 19th October 2012 at 03:23 PM.
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Old 19th October 2012, 04:52 PM   #1236
neb001 is offline neb001  United States
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Old 19th October 2012, 05:02 PM   #1237
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Quote:
Originally Posted by qusp View Post
I would be very surprised if EXA approached the levels of jitter possible with fifo,
Agreed, it's the reason i asked about the clocks. Have you been able to compare the supplied clocks to the Crystek. Is the audible difference dramatic?
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Old 19th October 2012, 05:18 PM   #1238
glt is offline glt  United States
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Here is a suggestion for the production Si570 board:

There has been some discussion of using a phase inverted master clock with the Sabre DAC. The Si570 has a Clk+ and Clk- output. One idea is to have both outputs for manual switching.

I don't know how this would make any improvements but it is a positive tweak that has been discussed.
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Old 20th October 2012, 01:04 AM   #1239
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Quote:
Originally Posted by glt View Post
Here is a suggestion for the production Si570 board:

There has been some discussion of using a phase inverted master clock with the Sabre DAC. The Si570 has a Clk+ and Clk- output. One idea is to have both outputs for manual switching.

I don't know how this would make any improvements but it is a positive tweak that has been discussed.
Hi glt,

I use Potato logic FFs on the 570 clock board. The Tpd=2ns. So, all of the I2S signals will be delayed 2ns after raising edge of MCLK. If feed reversed MCLK into ESS9018, take 98.xxx Mhz, the I2S delay will be 5.1+2=7.2ns, that's the only difference. Using slower HC FFs will get the same thing.

Is there any details about reversing 9018 MCLK?

Nice weekend.

Ian
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Old 20th October 2012, 01:36 AM   #1240
SPWONG is offline SPWONG  Hong Kong
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