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Old 11th October 2012, 12:37 AM   #1151
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Originally Posted by AR2 View Post
Awesome Ian!
When do we start placing orders? HeHe.
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Originally Posted by nicoch58 View Post
iancanada very very great work !!!
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Originally Posted by ed linssen View Post
Perfect solution, Ian!
Another beauty.
Ed
Thanks guys.

Ian
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Old 11th October 2012, 12:52 AM   #1152
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Originally Posted by iancanada View Post
Soft starting is a very good idea, especially for high current projects such as power amp PUS. Or, maybe a crazy IV stage in some cases . But that would be another design of high current version.

But please do not use soft start for the XO power, because most of digital applications need having clock running prior to other logic .

Ian
I was mostly thinking that the soft start would be addressing the high startup current of low impedance battery->low ESR cap rather than higher current during normal usage.

I think qusp is referring to say the nichicon R7 caps (and similar) as used for local bulk caps on PSU input of 'The Wire' headphone amplifiers for example. Relatively low current during normal usage, but at turn on the transient could easily exceed the current rating of these relays. Very good point about being certain that these delays are not imposed on clocks etc!

Thanks for yet another great design Ian, I think these soft start circuits (if necessary) could be achieved by stacking your current design and it is then a issue to be managed by the user with understanding of the circuits that they are supplying.

Chris
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Old 11th October 2012, 01:05 AM   #1153
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yep, thats what I meant, particularly if there are banks of 4 or more caps after the relay. But I agree, thats something for us to sort out; worth mentioning though, since I wouldnt put it past some members of this GB to put a stack of polymer or film reservoirs after a battery relay.
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Old 11th October 2012, 01:17 AM   #1154
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Originally Posted by hochopeper View Post
I was mostly thinking that the soft start would be addressing the high startup current of low impedance battery->low ESR cap rather than higher current during normal usage.

I think qusp is referring to say the nichicon R7 caps (and similar) as used for local bulk caps on PSU input of 'The Wire' headphone amplifiers for example. Relatively low current during normal usage, but at turn on the transient could easily exceed the current rating of these relays. Very good point about being certain that these delays are not imposed on clocks etc!

Thanks for yet another great design Ian, I think these soft start circuits (if necessary) could be achieved by stacking your current design and it is then a issue to be managed by the user with understanding of the circuits that they are supplying.

Chris
Thanks hochopeper, I like most of your ideas, very constructive.

I'll post the schematics, but I need some organizing...job.. It was a very quick design . I left some options on the PCB, so maybe, something is possible beased on different configurations with current PCB.

Regards,

Ian
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Old 11th October 2012, 06:10 PM   #1155
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Red face hookup tda1305

hello Ian,

I want to hookup a cs8414 in slave mode to a tda1305T .
May be you can tell me how to do?
The cs8414 outputs 32 bits and the TDA1305 in I2s mode can handle 20 bits.
I am affraid i overlook something.

greet Marius.
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Old 11th October 2012, 11:54 PM   #1156
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come on, couldnt you send this request by PM or something? its off topic in just about every way possible
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Old 12th October 2012, 10:41 AM   #1157
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I see the "sweetness and light" has gone out already..... ;-)

Marius, I know Ian is an incredibly helpful gent, patient and kind, however your question is way off base for what this thread is about.
Perhaps your own thread or do a search on others that use this combo, I haven't actually read of anyone mentioning this chip on this thread before.
Do you have the FIFO to use with this?

Sweetness and light restored......

qusp, slightly OT, sent you an email aboot batteries, did you get?

Thanks,

Drew.
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Old 12th October 2012, 04:29 PM   #1158
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Hi Ian

Actually regarding power for Dual Clock board.

I did small mod and tap ShuntReg directly to feed the XO's. Unfortunately cutting trace was required and that was the hardest part, to cut that beautifully crafted board. But at the end there is shunt reg for XO's and in my case I left switch to be able to test differences between on-board LDO and shunt-reg and next to have open solution to tap LiPo batteries.
Well can say that the results are at list interesting and even more interesting is comparing differences between TentClock and Crystek 957 powered by LDO and ShuntReg.
So it is fun... and seems that in my case Trident will stay.

But actually have two questions.

How about using CCHD 957 XO's Standby Mode ?
That seems to be interesting, we could shut down not used XO, and possibly that could reduce noise and interferences from running two clocks on the same board/power, that possibly matter even while they are nicely decoupled . Well also would lower the power required to run the XO's from batteries.
I have tested that board requires two clocks running to start up... so need Your help/advise with that.
Any back-door to use logic that is already on board to put unused Crystek XO in standby mode in the right time..?
Well and also to start it up during changing frequencies.

Second question is regarding power for fan-out chip's.

They are powered from flip-flops LDO and while MClk to DAC is send not directly from XO's but from fan-out chip's , its power can have influence on clock "quality".
I wonder of Your opinion regarding taping them to XO's shunt reg or XO's "free" LDO. But since that would require much more "surgery" on Your board I fought about asking Your opinion first, seems that You deliberately are using flip-flops LDO to power fan-out chips even while XO LDO is much closer.

Rosendorfer
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Old 16th October 2012, 12:08 AM   #1159
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Sorry for my absent last weekend. I was listening to music. The isolation board together with the battery management really made some difference to my system. Kind of enjoymentJ.

I guess testing group already start receiving the PCB. Here are some digikey P/Ns which I didnít list in the BOM. Just in case you need them.


PH2.0mm terminal pins: 455-1127-2-ND
2P PH2.0mm housing: 455-1165-ND
IC socket to pick up XO pin from: ED2681-ND

Iím looking forward to your good news.

Ian
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Old 16th October 2012, 01:15 AM   #1160
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Originally Posted by Rosendorfer View Post
Hi Ian

Actually regarding power for Dual Clock board.

I did small mod and tap ShuntReg directly to feed the XO's. Unfortunately cutting trace was required and that was the hardest part, to cut that beautifully crafted board. But at the end there is shunt reg for XO's and in my case I left switch to be able to test differences between on-board LDO and shunt-reg and next to have open solution to tap LiPo batteries.
Well can say that the results are at list interesting and even more interesting is comparing differences between TentClock and Crystek 957 powered by LDO and ShuntReg.
So it is fun... and seems that in my case Trident will stay.

But actually have two questions.

How about using CCHD 957 XO's Standby Mode ?
That seems to be interesting, we could shut down not used XO, and possibly that could reduce noise and interferences from running two clocks on the same board/power, that possibly matter even while they are nicely decoupled . Well also would lower the power required to run the XO's from batteries.
I have tested that board requires two clocks running to start up... so need Your help/advise with that.
Any back-door to use logic that is already on board to put unused Crystek XO in standby mode in the right time..?
Well and also to start it up during changing frequencies.

Second question is regarding power for fan-out chip's.

They are powered from flip-flops LDO and while MClk to DAC is send not directly from XO's but from fan-out chip's , its power can have influence on clock "quality".
I wonder of Your opinion regarding taping them to XO's shunt reg or XO's "free" LDO. But since that would require much more "surgery" on Your board I fought about asking Your opinion first, seems that You deliberately are using flip-flops LDO to power fan-out chips even while XO LDO is much closer.

Rosendorfer
Good job Rosendorfer! That's a wonderful experiencing.

PUS is very very important for the clock board. Please keep good working on the research, youíll get a lot of discovery. I have a spare TP shunt reg, maybe I can give a try when I get time.

The Dual XO Clock Board already has the XO standby control logic included. If you are running two CCHD951, one is working and the other one will be put into standby mode. Tentclock is the only one exception which doesnít come with a disable control.

XO is the most important part on the clock board, so itís better to have independent LDO. Distributing the clock via a funout buffer is a better solution. The additive jitter of the driver is only 29 fs. Please always avoid driving multiple loads or long cable directly from the output of XO which will lower grade the XO performance.

I have another solution which Iím using right now to power the dual XO board: Remove the two on board LDO and short the input and output with two 0 ohm 0805 jumpers (resistor). Then power the dual xo clock board with one 3.2V LiFePO4 battery cell (Iím having a passive battery management board now) from J5 DC input port, but you need an isolator board to avoid short with the FIFO power otherwise you have to remove L11.

Good luck to your project.

Ian
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