Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

Hi Ian,

I was just reading the ES9012 datasheet and found a paragraph on page 12 that might be interesting to you there is a paragraph titled: DPLL Frequency Phase Flip. Register 17 can be used to set the DPLL to lock to rising or falling edge of the clock.

In your experiments with Si570 inverted mclk have you been able to adjust that DAC Register also?


Cheers,
Chris
 
Hi Ian,

I was just reading the ES9012 datasheet and found a paragraph on page 12 that might be interesting to you there is a paragraph titled: DPLL Frequency Phase Flip. Register 17 can be used to set the DPLL to lock to rising or falling edge of the clock.

In your experiments with Si570 inverted mclk have you been able to adjust that DAC Register also?


Cheers,
Chris

Can you send me the pdf ? FIFO does not change the ESS register. If your have external control, you can give a try by software. I'm interested in your result.

Regards,

Iian
 
Flipping that around without changing the clock I wouldn't have expected night and day changes. The point I was making is that with inverted mclk from Si570 I think you might want the DPLL synching to the falling edge and for 'normal' mclk then rising edge would make sense.


See the scope shots of Ian's in Post #1606


Regardless I think we're getting to the thin end of the list of improvements perhaps already so all of the night and day changes are probably way back in the past.

Cheers,
Chris
 
yeah thats what he said, ie where he got the info from; as did I but if there is a difference I find it hard to elucidate. it was far from a controlled test though, just changing the register while audio was playing.

'the wire' plus JH13 in ears is a pretty good lens to pick changes. it did appear to change the sound slightly, but yes perhaps its best saved for si570 experiments

I did also flip the phase on titan
 
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Flipping that around without changing the clock I wouldn't have expected night and day changes. The point I was making is that with inverted mclk from Si570 I think you might want the DPLL synching to the falling edge and for 'normal' mclk then rising edge would make sense.


See the scope shots of Ian's in Post #1606


Regardless I think we're getting to the thin end of the list of improvements perhaps already so all of the night and day changes are probably way back in the past.

Cheers,
Chris

Asynch or synch?
 
sync, the idea is to play with the phase relationship between a synchronous inverted MCK input and an inverted/non-inverted phase DPLL

how could it be async? it wouldnt have an mck to input if it was async

I don't know the relationship between all the clocks. DPLL locks to bitclock in asynch. In synch, it is always "locked" to the bitclock
 
the idea is to have a an inverted phase MLCK (synchronous is from fifo) and also play with inverting (or not) the phase of the DPLL, which would naturally be synchronised/locked with the MCLK. 'locked' or not, it would still be in its default phase setting (upward/rising stroke) the idea is to see how beneficial it may be to switch that to the falling edge
 
the idea is to have a an inverted phase MLCK (synchronous is from fifo) and also play with inverting (or not) the phase of the DPLL, which would naturally be synchronised/locked with the MCLK. 'locked' or not, it would still be in its default phase setting (upward/rising stroke) the idea is to see how beneficial it may be to switch that to the falling edge

I know the intention of the experiment. What I don't know is how is "locking to rising or falling edge of the bitclock" (inverting or not inverting the phase of the DPLL) related to the master clock in synchronous mode
 
do you think the DPLL vanishes? still? the DPLL loop is still active, it just doesnt have a whole lot to do, it effectively does nothing, but it is not switched off.

there is no Sync mode, or Async mode on ESS, you can only present it with conditions that mean it acts synchronously

the point being, that perhaps one of them is cleaner.
 
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How did you connect the EXA to the fifo? Did you use the isolator board to isolate clock & reclocker & dac grounds from the digital input ground? Does exaU2I have the impedance matching resistors on outputs?


The EXA board has optical isolation at output. As there is no onboard reclocking following the isolators, they are probably the main source of jitter. Yet, having tried most of the USB/I2S boards in manufacture, the EXA is to my ears head and shoulders above the rest. Entirely subjective opinion, of course.
 
the idea is to have a an inverted phase MLCK (synchronous is from fifo) and also play with inverting (or not) the phase of the DPLL, which would naturally be synchronised/locked with the MCLK. 'locked' or not, it would still be in its default phase setting (upward/rising stroke) the idea is to see how beneficial it may be to switch that to the falling edge

As I understand, there is no any real PLL or VCO inside ESS DAC. My point might be wrong, but I think their DPLL concept is totally an ASRC algorithm, or could be looked upon as a kind of digital filter. At async mode, all data is calculated/estimated in 32bit resolution according to output of phase comparator. At sync mode (phase comparator output is 0), real data picked up from each Fs point and interpolating data placed in between to up-sample music into higher Fs. The accuracy determined by both DSP data length (32bit is highest so far) and the MCLK frequency. That why higher MCLK result in better SQ on ESS DAC.
Nobody knows the actual details except the designers. Besides, what we can do I think is just trust your ears to find out which way is better, MCLK inverting or normal, and software lock to raising or falling edge.

Ian
 
Hi Ian,

Makes a lot of sense.

I've observed the value of the 32-bit dpll in asynch mode and it varies quite a bit all the time. As one increases the bandwidth of the dpll, the variations get larger.

It may be obvious, but may I ask the question: in asynch mode with the inherent error from the DPLL value, is higher mclk frequency necessarily more accurate? or there is a sweet spot at certain frequency?
 
As I understand, there is no any real PLL or VCO inside ESS DAC. My point might be wrong, but I think their DPLL concept is totally an ASRC algorithm, or could be looked upon as a kind of digital filter. At async mode, all data is calculated/estimated in 32bit resolution according to output of phase comparator.

I have the similar speculations.

I've observed the value of the 32-bit dpll in asynch mode and it varies quite a bit all the time. As one increases the bandwidth of the dpll, the variations get larger.

It may be obvious, but may I ask the question: in asynch mode with the inherent error from the DPLL value, is higher mclk frequency necessarily more accurate? or there is a sweet spot at certain frequency?

There might be three aspects.

The MCLK frequencies of 512 x, 1024 x, 2048 x fs or near to these are apparently sweet spots as they create almost the same situations as a synchronous MCLK does.

The DPLL value register holds a count value of BCLK in 32 bit unsigned integer of which full scale, 2^32-1, matches to MCLK counts. The higher MCLK frequency is, the smaller the count value becomes. Therefore, a higher MCLK frequency should allow a lower DPLL bandwidth for the same fs.

ES9018 assumes the time interval given by MCLK is absolutely correct and constant. However, an actual clock has a certain fluctuation. The relative stability between BCLK and MCLK is important. The MCLK source of higher frequency tends to have the larger phase noise. There might be an optimum points.
 
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