Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 101 - diyAudio
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Old 18th September 2012, 01:32 PM   #1001
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It seems an odd design for the receptacle if that is all that note is about ... presumably it would become more of an issue with some insert/remove cycles on the connector leading to wear on that area below the receptacle.
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Old 18th September 2012, 02:46 PM   #1002
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Shorting is definitely a concern but I also recall being told something about rf something something considerations something.

Although that could just be my bad memory + talking to a certain square peg =P
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Old 18th September 2012, 03:31 PM   #1003
marce is offline marce  United Kingdom
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Solder resist should never be used as a barrier against shorts, a sinilar problem exists with these type of connectors:
http://www.hirose.co.jp/cataloge_hp/e53700036.pdf
I always use a keep out area under the connector again to avoid shorts!
Just recently used these connectors with a cc1000 transmitter, ground plane under connector on an inner layer. This is just basic LPD433 stuff though.
If you are putting antennas on board the story is different, and different frequency RF will have its own problems and layout requirements. The main thing with these connectors for full RF is to keep the trace to the connector from the transmitter/Reciever at 50 ohms, on a two layer board this is a quite a wide trace.
Checked another board with mobile connectivity, again ground plane complete under the rf connector.
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Old 19th September 2012, 12:58 AM   #1004
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Default Revised Si570 based clock board PCB V2.0

Quote:
Originally Posted by hochopeper View Post
Hi Ian,

1. The hirose datasheet suggests removing ground plane from beneath the signal portion of the u.fl receptacle (see attached extract from hirose datasheet), it looks like your boards have the gnd continuing through this area? Is this a concern? I am far from knowledgable on these things just asking a honest question here.
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The signalpart of the connector goes underneaath through that areato the central pin of the actualconnector, if the solder resist is a bit flakey it can short out. I would reccomend adding a keep out area to the actual footprint if your CAD package allows it, as it is one of those things you'll forget with this device otherwise, next time you use it! I know I have done in the past

Hi guys, good eye! PCB revised with route keepout. Please let me know for any suggestion. Thank you.

Ian
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Old 19th September 2012, 01:25 AM   #1005
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Quote:
Originally Posted by hochopeper View Post
Hi Ian,

The Si570 board progress looks very promising indeed! I have two questions though and I'm not sure if either or both have been covered previously.

2. Is it possible with the Si570 that the output stream may select a different *MCLK based on the input Fs?
Yes, it is. By taking the advantage of Si570, this board was specially designed with capability of output different MCLK frequency for a patiqular input Fs.


Quote:
I have a DAC (ES9023) that I would like to use Fs*512 for Fs<=96kHz and Fs*256 for Fs>96kHz. Is this a possible configuration option via serial port? I will have either a microcontroller or an arm based linux board in the DAC enclosure so will be able to leave either of those permanently connected to the FIFO kit for 3rd party control if necessary.
That would be another back door . It will make things even more interesting.

Ian
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Old 19th September 2012, 05:40 AM   #1006
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Thanks Ian,

Now I am really looking forward to reading about your results of the next batch of prototypes!

Chris
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Old 21st September 2012, 02:10 AM   #1007
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Default PCB layout of the FIFO digital isolator board

Except the isolators for bridging the FIFO and clock board, I placed a universal isolator at the empty space for some potential applications. That isolator chip could be IL715/IL716/IL717, or alternatives from Silicon Labs Si8440BB/Si8441BB/Si8442BB. The PUS could be independent from FIFO and clock on both sides by jumper settings.

It would be an interesting adapter. I might try to supply some free bare PCBs for evaluation after I get themJ.

Ian
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Old 21st September 2012, 02:45 AM   #1008
glt is offline glt  United States
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Nice. For this application, the Silabs devices are best choice because of their much lower cost.
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Old 21st September 2012, 07:49 AM   #1009
qusp is offline qusp  Australia
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excellent ian, do you think it will handle DSD? just thinking I might like to try one with the amanero Combo384 board
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Old 21st September 2012, 11:09 AM   #1010
NicMac is offline NicMac  Italy
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Quote:
Originally Posted by iancanada View Post
It would be an interesting adapter. I might try to supply some free bare PCBs for evaluation after I get themJ.

Ian
I would be interested in trying one out. Not that I care if free or at cost, but because I would like to play with the isolator
BTW is there an ETA for the Si570 clock board?

Cheers,

Nic
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