I have been reading some interesting posts about slew-rate induced distortion in SPDIF receivers & input circuitry & wondered about how general this effect might be & might it be one mechanism that explains how different SPDIF cables effect the sound?
Has anybody got any information on the slew rate of the common SPDIF receiver chips &/or input circuitry?
Here's some info I lifted from Audiocircle posted by Jneutron that gives a good overview (in this case he is talking about RF attenuators but you can extrapolate):
Has anybody got any information on the slew rate of the common SPDIF receiver chips &/or input circuitry?
Here's some info I lifted from Audiocircle posted by Jneutron that gives a good overview (in this case he is talking about RF attenuators but you can extrapolate):
Interesting.
I've talked a lot to people like Guido Tent, known for his low-jitter clocks, and apparently the secret is in the loop response of the pll.
If the bandwidthg of that loop is wide enough to accomodate the jitter spectrum of the signal, it is nulled out. That would mean that with a good pll S/PDIF jitter would be nulled out.
However, I do not claim to be an expert on this so will yield to the real experts.
jan didden
I've talked a lot to people like Guido Tent, known for his low-jitter clocks, and apparently the secret is in the loop response of the pll.
If the bandwidthg of that loop is wide enough to accomodate the jitter spectrum of the signal, it is nulled out. That would mean that with a good pll S/PDIF jitter would be nulled out.
However, I do not claim to be an expert on this so will yield to the real experts.
jan didden
Cable problems generally cause high frequency jitter. The PLL is designed to filter out high frequency jitter, so all you should be left with is the low frequency jitter coming from the CD player clock. The PLL acts as a low pass filter, so you want low bandwidth to filter out as much clock jitter as possible.
Reducing slew rate may reduce cable reflections, but can increase jitter in the receiver data slicer so there may be a need to adopt the best compromise. My guess is that the cable rise times should not be much greater than the response time of the data receiver: slower rise than this causes receiver-generated jitter, faster rise than this causes cable reflection jitter. Of the two, receiver-generated jitter is probably worse because it could include low frequencies which the PLL cannot filter out. So err on the side of more cable jitter - which may be the opposite of what some people say!
Reducing slew rate may reduce cable reflections, but can increase jitter in the receiver data slicer so there may be a need to adopt the best compromise. My guess is that the cable rise times should not be much greater than the response time of the data receiver: slower rise than this causes receiver-generated jitter, faster rise than this causes cable reflection jitter. Of the two, receiver-generated jitter is probably worse because it could include low frequencies which the PLL cannot filter out. So err on the side of more cable jitter - which may be the opposite of what some people say!
I agree... the new receivers PLL loop and new DAC's internals can filter the high frequency jitter easily.
The low-frequency jitter, produced by the transport mechanism itself, is the hardest to "fix".
I would say that the "too high slew-rate" is not a concern if are used newer chips (both in receiver and DAC sections).
The low-frequency jitter, produced by the transport mechanism itself, is the hardest to "fix".
I would say that the "too high slew-rate" is not a concern if are used newer chips (both in receiver and DAC sections).
I believe some of the things I've seen from Guido are PLLs that filter from below 100Hz upward. And no, I don't work there and have no shares in the company
jan didden
Been away for a little rest so couldn't comment
But what I hoped to follow up was the idea/premise, if I understand correctly, that fast rise time in SPDIF signals can cause non-linear distortions in SPDIF receivers because they are slew rate limited.
So this gives rise, in my mind, to some questions:
- what do people think of this? the posts above don't seem to address this, dealing more with PLL distortions.
- Any ideas what is the slew rate limits of the input stages of various SPDIF receivers?
- The advantage of faster rise times is that inter-symbol jitter is thought to be reduced - is this advantage offset by the above distortion mechanism?
Probably difficult questions to answer & maybe no definitive answers are possible but worth investigating?
But what I hoped to follow up was the idea/premise, if I understand correctly, that fast rise time in SPDIF signals can cause non-linear distortions in SPDIF receivers because they are slew rate limited.
So this gives rise, in my mind, to some questions:
- what do people think of this? the posts above don't seem to address this, dealing more with PLL distortions.
- Any ideas what is the slew rate limits of the input stages of various SPDIF receivers?
- The advantage of faster rise times is that inter-symbol jitter is thought to be reduced - is this advantage offset by the above distortion mechanism?
Probably difficult questions to answer & maybe no definitive answers are possible but worth investigating?
I really shouldn't but...
There sure are a lot lot of "I think"s and "I believe"s in this thread and no actual references.
Time Distortions Within Digital Audio Equipment Due to Integrated Circuit Logic Induced Modulation Products
Authors: Meitner, Edmund; Gendron, Robert
AES E-Library Time Distortions Within Digital Audio Equipment Due to Integrated Circuit Logic Induced Modulation Products
Slew rate is not exact relevant for logic circuit since they digital circuits and not analog. That said, I will agree that you can have logic transitions that are too fast. The faster the edge rate the more attention to termination and decoupling that is required. Excessive switching speed will induce ground bounce, ringing, and RF noise in the digital circuitry which can induce jitter in the S/P-DIF interface. Reflections from improper impedance matching, pulse transformers, connectors, wire termination techniques, receiver hysteresis ( comparators use hysteresis to increase switching speed and increase noise reflection), and common mode noise between the digital source and the DAC make this interface a job left the a good RF designer. I have measure digital cable with impedance between 50 and 120 ohms and DAC S/P-DIF inputs from 35ohms to 150 ohms for interface that is specified to be 75 ohms. Putting a 50 ohm BNC connector with a few inches of 110 ohm twisted pair to the input receiver is typical. I get amused when everybody runs around screaming that the whole concept of the S/P-DIF interface is flawed when see its half *** implementation in a DAC costing five thousand bucks
For further details on logic Signal Integrity.
Signal Consulting, Inc. - Dr. Howard Johnson
There sure are a lot lot of "I think"s and "I believe"s in this thread and no actual references.
Time Distortions Within Digital Audio Equipment Due to Integrated Circuit Logic Induced Modulation Products
Authors: Meitner, Edmund; Gendron, Robert
AES E-Library Time Distortions Within Digital Audio Equipment Due to Integrated Circuit Logic Induced Modulation Products
Slew rate is not exact relevant for logic circuit since they digital circuits and not analog. That said, I will agree that you can have logic transitions that are too fast. The faster the edge rate the more attention to termination and decoupling that is required. Excessive switching speed will induce ground bounce, ringing, and RF noise in the digital circuitry which can induce jitter in the S/P-DIF interface. Reflections from improper impedance matching, pulse transformers, connectors, wire termination techniques, receiver hysteresis ( comparators use hysteresis to increase switching speed and increase noise reflection), and common mode noise between the digital source and the DAC make this interface a job left the a good RF designer. I have measure digital cable with impedance between 50 and 120 ohms and DAC S/P-DIF inputs from 35ohms to 150 ohms for interface that is specified to be 75 ohms. Putting a 50 ohm BNC connector with a few inches of 110 ohm twisted pair to the input receiver is typical. I get amused when everybody runs around screaming that the whole concept of the S/P-DIF interface is flawed when see its half *** implementation in a DAC costing five thousand bucks
For further details on logic Signal Integrity.
Signal Consulting, Inc. - Dr. Howard Johnson
Agreed, but it's an area that hasn't been addressed in the literature - I believe
Thanks for the reference on logic induced modulation but this is a different meachanism!
Have to disagree with you here! The SPDIF signal has a P-P voltage over a certain rise time = a slew rate. If the input circuit of an active device is slew rate limited then distortion will enter the system at this point. I'm trying to tease out the parameters & possible effects of this potential distortion.
Agree completely with your views on RF & the implementation issues you encountered in digital audio. What I was hoping to start was a discussion on a potentially new SPDIF problem not identified in the Dunn & Hawksford paper Is the AES/EBU-S/PDIF Digital Audio Interface Flawed?
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I am reminded of the quote "Everyone talks about weather but no one does anything about it." Rise time and slew rate are not really the same thing. I will leave new distortion mechanisms to the "academics" since no one seems very interested in fixing the known ones. Not trying to be insulting but these discussions go nowhere without some solid engineering knowledge and in this case, experience with digital signal integrity.
Back to your regularly scheduled discussion.
Back to your regularly scheduled discussion.
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But with digital and signal integrity I'd say that rise time, not slew rate is the correct term, rise time is also specified at either 10%-90% or 20%-80% (IBIS spec).
A few more Si based links, there is a lot of info and research done regarding SI problems with digital interfaces.
beTheSignal.com
Design for Signal Integrity: Unit 02 Integrity of Digital Signals
Speeding Edge consultants specialize in high-speed PCB and system design disciplines
Welcome
A few more Si based links, there is a lot of info and research done regarding SI problems with digital interfaces.
beTheSignal.com
Design for Signal Integrity: Unit 02 Integrity of Digital Signals
Speeding Edge consultants specialize in high-speed PCB and system design disciplines
Welcome
Hi Marce, yes but in any active device that is acting as a receiver is the ability to return the input stage to zero in readiness for the next signal not important?
In other words, SPDIF has a spec of ~0.5V P-P & the faster SPDIF transmitters will do this in 1-2nS.
I'm just asking the question - how well does the active circuitry in DAC devices deal with this slew rate?
I was hoping some of the digital experts here might be able to provide detail on this - the datasheets don't seem to address this.
In other words, SPDIF has a spec of ~0.5V P-P & the faster SPDIF transmitters will do this in 1-2nS.
I'm just asking the question - how well does the active circuitry in DAC devices deal with this slew rate?
I was hoping some of the digital experts here might be able to provide detail on this - the datasheets don't seem to address this.
In our case for just about every digital interface that we think is critical, we us Signal Integrity Verification software, with manufacturers IBIS models. We can model connectors, leads, the PCB layouts etc. We can simulate the effect of jitter etc etc.
We have found its the only way these days to guarantee a less problematic layout and system. So I will spend hours (literaly) simulating a section of layout to get the desired results and finding the best balance between rise times, and signal path. The use of these SI tools is increasing as it is becoming so critical with the faster rise times.
I'll have a llok around some data sheets later if I get time, though we use mainly Ti codecs.
We have found its the only way these days to guarantee a less problematic layout and system. So I will spend hours (literaly) simulating a section of layout to get the desired results and finding the best balance between rise times, and signal path. The use of these SI tools is increasing as it is becoming so critical with the faster rise times.
I'll have a llok around some data sheets later if I get time, though we use mainly Ti codecs.
Thanks Marce, appreciated!
I first encountered this in using the Hiface which has a high 5VP-P & rise time of ~2nS. Using an RF attenuator of 20dB to bring the signal down had a major benefit to the sound. Lower value RF attenuators have since been tried on many SPDIF devices (most within spec) & have been found to benefit the sound in almost all cases. The theory of operation of these attenuators is that they reduce reflections but there is also the above possibility. I'm just interested in finding out some more about this - it may lead to better understanding of the SPDIF & it's vagaries?
I first encountered this in using the Hiface which has a high 5VP-P & rise time of ~2nS. Using an RF attenuator of 20dB to bring the signal down had a major benefit to the sound. Lower value RF attenuators have since been tried on many SPDIF devices (most within spec) & have been found to benefit the sound in almost all cases. The theory of operation of these attenuators is that they reduce reflections but there is also the above possibility. I'm just interested in finding out some more about this - it may lead to better understanding of the SPDIF & it's vagaries?
SPDIF is a consumer interface for the transfer of digital signals, it is inherently wrong to multiplex signals when you do not have to. I had published in Electronics World in June of 1997 an article concerning overcoming the deficiencies of SPDIF. It was kindly reprinted by enjoy the music
The Deficiencies of SPDIF as a Digital Transmission Method
The answer is to use flip flops to store and transfer independently each of the three signals
namely BITCLOCK DATA and LRCK and at reception clock these same signals using flip flops on to the oversampling filter where by coincidence BITCLOCK DATA and LRCK are
available as inputs.
Cheers / Chris
The Deficiencies of SPDIF as a Digital Transmission Method
The answer is to use flip flops to store and transfer independently each of the three signals
namely BITCLOCK DATA and LRCK and at reception clock these same signals using flip flops on to the oversampling filter where by coincidence BITCLOCK DATA and LRCK are
available as inputs.
Cheers / Chris
Sure Chris, SPDIF is flawed & it's best to avoid it altogether if possible - I use I2S when I can but this needs to situated very close to the DAC which isn't always possible. There is of course differential I2S to overcome the distance limitations.
But my interest here is to investigate one particular issue which may have a bearing on the performance of SPDIF interfaces - slew rate distortion & the possibility of it being an issue!
Hi jkeny
This article provides insight into slew rate distortion - aka jitter
Jitter & the Digital Interface | Stereophile.com
Cheers / Chris
This article provides insight into slew rate distortion - aka jitter
Jitter & the Digital Interface | Stereophile.com
Cheers / Chris
Thanks, but I don't think it mentions anything about slew rate distortion in the SPDIF input circuitry. The Hawksford & Dunn paper is about the most comprehensive treatment of jitter I've read http://www.scalatech.co.uk/papers/aes93.pdf but again it doesn't cover this possible distortion mechanism!
"This article is a primer on jitter in digital audio. We will look at what jitter is, its causes, effects, and how jitter can be reduced. The article is divided into four main sections: 1) jitter is defined and its properties examined; 2) jitter's impact on sonic performance is theoretically derived, both for multi-bit converters and so-called "1-bit" or "noise-shaping" converters; 3) the AES/EBU and S/PDIF interface is analyzed, revealing that the interface is the primary jitter source when not properly implemented; and 4) a method of measuring jitter is presented, along with test results on CD transports that show large differences in their jitter performances."
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