Help: Strong images mirrored around Fs/2

[RocketScientist]

Perhaps someone who knows oversampling digital filters can help me out with this one. I'm working with a DAC using an Analog Devices AD1852 Sigma-Delta high-end DAC with a fairly textbook reconstruction/low-pass filter right off the datasheet. The AD1852 doesn't have many options and it's being fed by a TI DIR9001, and from what I can figure out, the oversampling factor (i.e. 64X, 128X, etc.) is supposed to sort itself out based on what the DIR9001 is receiving. This is a commercial design.

There are strong images mirrored around the Nyquist frequency (Fs/2). With Fs=44.1 Khz, you get:

• 21,900 hz -3 dBFS input yields a 22,200 hz image at -4 dBFS
• 21,500 hz yields a 22,600 hz image at -12 dBFS
• 21,000 hz yields a 23,100 hz image at -30 dBFS

Here's the spectrum of the above 3 sine waves (on the left half) and their images in matching colors above 22,050 hz.



The oversampling filter doesn't seem to be working properly, but why not? At Fs=48 Khz and Fs=32 Khz it does the exact same thing. Has anyone seen this sort of thing before? I have to admit I haven't.

[abraxalito]

I first saw this with Philips 'Bitstream' SAA7321 chips over 20 years ago.

I just had a quick peek at ADI's datasheet for this part - your plots do look to be in keeping with the published filter responses, although the graphs are not shown in very high resolution around the nyquist frequency. So yes, it is working as advertised - the stop band only begins at 24.1kHz where they say -110dB.

Its a not-very well known problem I must admit, but I think Peter Craven and Bruno Putzeys have been aware of it for some time

[RocketScientist]

@abraxalito Thanks for the reply and help. I was at a loss to explain how the implementation of the AD1852 was to blame. So if it's normal behavior, that makes sense. I guess, all to often, we only see spectrums that stop at 20 or 22 Khz hiding such behavior.

That said, these DACs are obviously not the best choice for sampling rates < 44 Khz. And the AD1852 data sheet claims stop-band attenuation of 110db past 24.1 Khz. Yet here's an image at 25,100hz that's only attenuated about half that or 55 dB. So I'm not sure how you verify a DAC meets the stop band attentuation spec?



As for Bruno, I've met him a few times. He's a seriously bright guy and his powered speakers are impressive.

[abraxalito]

You're welcome

Its normal behaviour because these kinds of designs use 'half-band filters' to save on silicon real-estate. It reduces the number of multiplies by a factor of 2 because every other coefficient is zero in the FIR stage. Its one of the reasons I'm currently working on my own digital filter, which I'll talk about on my blog when I've got progress to show

Is the reason these parts wouldn't be good for <44k1 in your mind because those nasty images would very quickly become audible? I hadn't thought of that but its a good point! You'll find most, if not all digital filter chips are designed in this way, using half-band filters.

[RocketScientist]

I can safely say the Wolfson DAC's I've worked with don't suffer this problem. Neither have the ESS parts or even the lowly DAC built into the TI PCM27xx and PCM29xx parts. Analog Devices is apparently doing something different (perhaps for good reasons)?

See my added 2nd spectrum above. Even within the stop band the attenuation isn't anywhere close to the 110 dB claimed. But I'm not sure how the "110 dB" is really measured?

And yes, the nasty images could be audible (at least if you had good hearing) with Fs = 32 Khz.

[abraxalito]

Ah, thanks for the heads-up on that, I hadn't looked closely enough at WM8740 - I see its -3dB point is 0.491fs which doesn't qualify for being a half-band filter. But that's not early enough to ensure absolutely no aliasing - it will exhibit some images just not to the degree of ADI's part.

That spur of 25.1kHz has me concerned that maybe you've not got the sample rate bits (pins7,10) set up correctly on the chip. I've never known ADI lie on their datasheets and for this part it clearly says at least 110dB rejection above 24.1kHz (table 6). Just by eyeballing the graphs, the filter slope for 192kHz could match what you're seeing.

[RocketScientist]

Thanks. That would make sense if it's applying the filter for a higher sample rate. But I thought that was being handled...

The TI DIR9001 has 2 outputs (FSOUT0 and FSOUT1) that are supposed to indicate the sampling rate. But the table on page 24 of the datasheet only lists 32/44/48 Khz even though the DIR9001 handles up to 96 Khz. So I'm a bit puzzled what those pins do with an 88 or 96 Khz signal?

My best guess is the FSOUT pins on the DIR9001 are controlling pins 7 & 10 on the DAC to program the sample rate. But this isn't my design. So I would have to risk some fine pitch SMT probing to check the actual state of those pins when it's decoding various sample rates.

And the DIR9001 is already adjusting MCLK based on the input sample rate. While the AD1852 claims to have "clock auto divide" that's supposed to figure out the multiplier from MCLK and the I2S bitstream. It's also supposed to be a "glueless" DAC that can be directly interfaced to a variety of sources.

So I'm still a bit confused unless the AD1852 requires a MCU to switch the sample rate selection in a multi sample rate design? If so, we've found the problem because this design has no MCU!

[abraxalito]

Originally Posted by RocketScientist

The TI DIR9001 has 2 outputs (FSOUT0 and FSOUT1) that are supposed to indicate the sampling rate.

You'll want to check first if the design has the 24.576MHz crystal fitted - if not, those outputs will do nothing.

But the table on page 24 of the datasheet only lists 32/44/48 Khz even though the DIR9001 handles up to 96 Khz. So I'm a bit puzzled what those pins do with an 88 or 96 Khz signal?

They give the out of range condition in all cases except 32-48k - L H (0,1).

My best guess is the FSOUT pins on the DIR9001 are controlling pins 7 & 10 on the DAC to program the sample rate. But this isn't my design.

That configuration may be what's there but there's no way it'll work properly if so. The AD chip wants to know how many stages of FIR-based oversampling to use based on those pins, within the narrow range 32-48k it'll use the full 8X.

So I'm still a bit confused unless the AD1852 requires a MCU to switch the sample rate selection in a multi sample rate design? If so, we've found the problem because this design has no MCU!

I'm sure a CPU isn't a requirement, but an accurate indication of the input sample rate above 48k is. The DIR9001 appears not able to offer that. Not a marriage made in heaven methinks

[Jakob2]

@ RocketScientist,

as Abraxilito pointed out, it is most probably an issue due to improper clock or mode selection.

Of course probing of a fine pitch in powered state can be dangerous, but first it would help to examine the connections between the pins in unpowered state.

Check if the external clock is provided (abraxilito mentioned it) and than check if the FSOUT pins of the DIR9001 are hardwired to the interpolation ratio setting pins of the AD1852.
If the pins are hardwired, then the selection for the 44.1 kHz sample rate will work, but the coding for 32kHz will lead to a not allowed condition of the AD1852 as 192kHz and 96kHz mode would be enabled at the same time (both pins set to high level)

Additionally check the pins for the selection of the multiplication ratio of the DIR9001 as the AD1852 requires at least a 256x masterclock for a sampling rate of 48kHz and below.

[RocketScientist]

First of all, this is one reason I love diyAudio. I post an oddball question and within a couple posts the mystery is solved.

Thanks Abraxilito. There is no XTI clock on the DIR9001 as it's running in PLL mode. I earlier read FSOUT1&2 are "always enabled" but I see you're correct, the "frequency calculator" requires the XTI clock. In hindsight, that makes sense. So those pins are useless.

And thanks Jakob2. Ding! We have a winner! With some careful probing, it turns out both PSCK1 and PSCK2 on the DIR9001 are tied low which, per the datasheet, yields an SCKO of 128Fs! I verified this by checking the SCKO pin with a 44.1 Khz signal... it's only 5.65 Mhz. So the AD1852 is being severely "underclocked".

And the AD1852's 96/48 pin is tied high forever locking it into 96 Khz mode. That explains a lot as well.

I was far too trusting the manufacture would at least connect the dots and follow the basic datasheet requirements. But after some of my experiences with "audiophile" gear, I should know better. This could be another case of someone "designing by ear" which has gotten NuForce into similar trouble several times.

It's kind of amazing there are not more obvious problems. If someone measured this design with a typical RMAA set up they'd never even see anything wrong.

So I'm left to wonder if this was done on purpose somehow in the interest of "better sound", if it was done for some other reason not yet obvious to me (perhaps the PCB layout can't handle a 22+ Mhz clock?), or if it's a half baked design where someone really didn't know what they were doing?

I need to do some more investigation first, but this product may well end up on my blog as another example of why it's good to make the right measurements. Someone needs to keep the manufactures honest.

Thanks again to both of you for the help.