Cirrus Logis 8416 - 4354 Question

[CRST]

I have prototyped an S/PDIF DAC circuit using the Cirrus Logic 8416 / 4354 DAC. I've based it on Cirrus Logics reference design, contained on page 8 of the following document.

http://www.cirrus.com/en/pubs/rdData...DB4354_DB1.pdf

This circuit has 220 ohms of resistance in series with the 8416 output lines - SDOUT, OSCLK and OLRCK. Why? Why not just wire directly. I've done that on my prototype, and it seems to work.

Any hints are greatly appreciated.

Regards,
Richard.

[ihear21khz]

I believe that the resistors are there to remove the pulse undershoot that occurs. Some Filter and DAC chips don't seem to like this. A close associate has experimented by adding anything between 47ohms and 150ohms in clock lines (where these resistors were otherwise not installed) and found that adding a small resistance almost always improves the sonics of the DAC.

[CRST]

Thanks. I should be able to see that on the scope. I'll take a look. It may not be obvious on my breadboard setup - it breaks all the layout rules.

I'll lay the PCB out with these resistors included.

[Ken Newton]

Yes, such resistors would be there for the reason ihear21kHz suggests. They reduce jitter by reducing ground-bounce and ringing, and also by limiting the current spikes disturbing the power supply pins of individual chips.

[CRST]

OK. I have built up the circuit referenced above - with data line resistors. But, I have a problem.

With initial power up, the 8416 / 4354 combination outputs a 6093Hz signal onto both audio outputs - at about -58dB. There is also higher frequency noise - at about 80dB down. Once I apply an S/PDIF input (play the CD), this signal and the high frequency noise disappear. Neither reappears when the input is stopped, and total noise floor goes down below -95dB. (I can't measure any lower). Any ideas?

Unfortunately, I didn't notice this issue before I built up my PCB - so now I have the problem on both the breadboard and PCB. The layout between the two is quite different, but the circuit is the same.

Richard

[CRST]

OK. After some time off to visit with the flu...

I took another run through the data sheets and a close look at what was happening, as follows:
1. When the 8416 does not have an input signal (the CD is not playing), the VCO, and therefore MCLK runs at 750KHz. When the CD plays, it runs at 11.29MHz.
2. The 4354 contains an inverting charge pump - to provide negative rail for output. This appears to be clocked off MCLK. It runs at ~200KHz when MCLK is at 11MHz, and 12.5KHz when MCLK is at 750KHz. I suspect this is the source of the ~6KHz spurious signal. The 4354 is rated for clock frequencies between 7.6 and 55MHz. If that's the case, they probably should have disabled the charge pump at lower frequencies.
3. The spurious signal is actually 20db lower on the PCB version than the prototype. So, layout clearly does appear to have impact.
4. I also discover that I did not adhere to a couple of the layout guidelines. Note to self. Check PCB design guidelines after layout, as well as before. I'm going to try to modify the PCB to see if I can improve it.
5. There was no change I could make to the prototype that had any impact at all. I have to run in hardware mode. In software mode, I could control the VCO, and avoid the problem.

If the PCB mod doesn't work, I'll just have to try a different DAC.

Any other insights are most welcome.

[prairiemystic]

I checked an CS8416 circuit I have and with no input, MCLK just stays high or low and the NVERR pin asserts a mute relay. There is no output when the PLL is unlocked. Running in H/W mode, OMCK floating, C&U to VD; RCBL,96kHz,AUDIO to GND.
You could check your clock switching mode Cirrus Datasheet CS8416_F3.pdf (see 8.2 OMCK System Clock Mode), but it looks like you need another oscillator feeding OMCK to switch to when the PLL is unlocked.

[CRST]

I had the clock switching mode turned off - OMCK tied to GND. I also have U tied to GND. That selects a clock multiplier of 256. I did try with it set to VD. The 4354 stopped working. Not surprising since a x128 multiplier results in MCLK at 5.6MHz, and that part supports a minimum of 7.6Mhz.

I also tried a different DAC - Wolfson WM8726. No spurious signal there - the output is clean.

An external clock may be possible. Another alternative would be to just gate MCLK with NVERR. NVERR is always high when there is no signal and the VCO is down to 750KHz. Not sure what other issues that may cause. Or, I can relayout with the WM8726.

I'll try to clean up my existing layout. If that doesn't help, I'll I have to junk my PCB and redesign. It's a shame that the 4354 doesn't have a mute pin - I could just connect NVERR to that!

[CRST]

Cleaning up my PCB layout had no effect. I'd be curious to know if the spurious signal is present on Cirrus Logic's 4354 (CDP4354) eval board. Not that I'm about to spend over $400 to find out.

Surface mount is hard to desolder!!

[CRST]

I proto'd the gate on MCLK idea and applying a 12MHz clock to OMCK. Both worked - the DAC no longer generated the spurious 6KHz nor the high frequency noise when idle. The external clock solution resulted in slightly lower noise than the gate idea, so I will go with that.

Rather than junk the PCB, I'll just hang the crystal oscillator off the top. Not pretty, but seems to work well.

I'm not sure why I have a apply a clock just to shut the DAC up.