Digital Receiver Chips

[TomHinton]

Has anyone observed, Cirrus Logic CS8416 sounds better than AKM or any others? Assume all topology parameters have been optimized.

[DF96]

Which bit of Analog Line Level confuses you?

[pinkmouse]

Originally Posted by DF96

Which bit of Analog Line Level confuses you?

Thread moved.

[jean-paul]

CS8416 is of mediocre quality, DIR9001 is a lot better but I think Wolfson WM8805 is the best. It is the only one that has very low jitter specs and does reclocking too. There are very cheap modules onm Ebay with WM8805. I bought one to test the WM8805.

[SoNic_real_one]

WM8804/05 has the same jitter (in specs) as DIR9001: 50ps.
CS8416 has 200ps in the specs.

It was a discution somewhere on this forum about the WM8804/05 and if it contains or not the buffer memory that was described in their white paper (buffer necessary for the proper reclocking/de-jittering). I did say there:

I think they did implement the fractional PLL, but I didn't see any reference in the 8804/05 to the absolutelly necessary FIFO buffer described in the white paper.
Actually, they say "S/PDIF recovered clock using PLL, or stand alone crystal derived clock generation."
The device described in the white paper would be having the word and there.
Also in the datasheet they don't say nothing about a buffer. External clock it just "helping" the PLL loop, but the loop is still specified as beeing locked on the incoming signal.
The buffer would allow the asyncron functionality of the receiver, decoupling the input PLL loop from the XTALL generated output.

[jean-paul]

DIR9001 really is better than CS8416 despite the same jitter specs. No doubt about that, just compare them in real life. I have a hard time deciphering both datasheets as they seem to be written to create confusion. I know of some designers that thought DIR9001 needs a low jitter clock to do reclocking just because the datasheet is so vague in that aspect. Also both datasheets describe jitter specs differently so don't trust specifications on paper. It turns out that adding a low jitter clock to DIR9001 does not make any difference as it locks onto the incoming SPDIF stream with its PLL just as all other chips do. Nothing new except maybe for tighter specs.

WM8805 does reclocking and dejittering when a low jitter clock is used and jitter is the same on paper as DIR9001 so why not try it ? It is the only one chip solution at this moment that can do that together with its brother WM8804. I have not used WM8805 yet but I ordered some ready built units with WM8805 and I hope it lives up to the expectations. When it functions as decribed and as told by those that tried it the chip is one of the very best that has been developed til now. I ca not help to think it does true reclocking reading the (also) complex datasheet.

[SoNic_real_one]

I am curious about that too - I just don't have the equipment to test it.
Also, CS2300 looks like an interesting option to follow a digital receiver -it cleans the incoming jitter and supposelly has 50ps in band jitter.

[jean-paul]

It seems Crystal made their classic CS8412 very good, most of the chips that came after it are less good in performance. Don't take my word for it, I am just a simple hobby guy and by no means an expert with the right equipment to measure such specs.

[TomHinton]

Originally Posted by DF96

Which bit of Analog Line Level confuses you?

Sorry, I inadvertently clicked the wrong link.

[TomHinton]

The CS8412, CS8414, CS8415 were notorious for "losing their place". Digital In had to be unplugged, then plugged back in while music was playing to fix.