That was my point. I read somewhere that distortion increases in ASRC if sample rates are nearly equal. Any thoughts?
Some posts are too interesting to be lost: http://www.diyaudio.com/forums/digi...back-new-cs8421-high-res-asrc.html#post528312
I quote the most important part from Bruno Putzeys' post:
"The TI SRC4192 has several PLL settings among which it chooses depending on the amount of jitter present on the input. For normally low amounts (anything we'd practically encounter) of jitter, it has a narrow mode where the ratio estimation register is updated only once every few seconds. This means that between updates the conversion factor is held absolutely constant (ie it operates like a synchronous src), and none of the input jitter makes it to the output at all."
Emphasis is mine.
I quote the most important part from Bruno Putzeys' post:
"The TI SRC4192 has several PLL settings among which it chooses depending on the amount of jitter present on the input. For normally low amounts (anything we'd practically encounter) of jitter, it has a narrow mode where the ratio estimation register is updated only once every few seconds. This means that between updates the conversion factor is held absolutely constant (ie it operates like a synchronous src), and none of the input jitter makes it to the output at all."
Emphasis is mine.
Well, you asked if some chips were better than others...
Anyway, read pt 2 of the reply here for your last question: PSW Recording Forums: Bruno Putzeys (Designer) - Dave Hecht (Master Tech) => SRC based DACs, how bit-transparent are they?
Anyway, read pt 2 of the reply here for your last question: PSW Recording Forums: Bruno Putzeys (Designer) - Dave Hecht (Master Tech) => SRC based DACs, how bit-transparent are they?
Based on the above reference, it appears there is an advantage to having output rate not be any standard SR. The AD1896 data sheet states the part has tables for certain ratios, and that in-between ratios are interpolated from them. So far, no one has revealed what ratio the tables represent. Seems reasonable to pick a non-standard rate that would have a ratio equal to one of the tables. Is there any info on this?
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Which part of the datasheet are you referring to? In the description of its operation (pages 19,20) I can't see it talking about 'tables'. Do you mean the ROM coefficients?
I think your question about distortion where the input and output sample rates are almost identical is answered in the last paragraph of page 20. When they're almost the same, the fs(in)/fs(out) ratio is held fixed by the built-in hysteresis and this stops distortion occurring.
Tom,
This won't be a direct answer to your question, simply because I don't know the answer. However, I would like to make a few points which may ease your concern - yes, I know, concern is the middle-name of most of we audiophiles:
First, all digital filters, which is what an ASRC chip does, are lossy. Meaning, they will distort the signal passing through them.
Second, the distortion added by the AD1896 is low in the extreme. It DOES vary a little by the particular conversion ratio involved, but remains around the -140dB level.
Third, the AD1896 datasheet shows several example conversion rations, from greater than 1:1 (interpolation), to less than 1:1 (decimation). All performance graphs show nearly the same very low level of distortion, so you can likely assume this to be true for any arbitrary "in-between" ratios. This doesn't necessarily mean that there is not some golden ratio, but even if there were, I seriously doubt that anyone could hear the a difference in distortion going from -140dB to some even lower figure.
I not sure that you a drawing the correct conclusion about about the SRC4192's jitter performance, but it's also possible that I've misunderstood the point you are making. The ratio-estimator block is the key to the strong jitter suppression of ASRC. It act as a phase-noise filter by averaging a great many input samples to determine their long-term rate. This phase-noise filtering is actually a side-benefit of rate-estimation for the purpose of arbitrary sample-rate conversion, but none-the-less enables ASRC to greatly reject incoming sample jitter.
I admit that I'm not as familiar with the SRC4192 as with the AD1896. In the AD1896, the "narrow-mode" increases the jitter rejection of the device by increasing the number of samples used in the rate-estimation average rather than by reducing the number. Just because a given conversion ratio might be held constant doesn't necessarily also mean that the incoming and outgoing rates are now synchronous - by which I mean, rational.
The jitter rejection ability of the SRC4192 has always been suspect for me because the jitter transfer mask is not depicted in it's datasheet - as of the last time I looked. Given that the SRC4192 is essentially intended as a replacement for the AD1896, it makes me doubly suspicious that a jitter transfer mask is not shown.
SRC4192 eliminates the jitter using the 64 samples buffer memory for normal delay or 32 samples for short delay. Data path is 28 bit wide.
AD1896 has 64 samples for long delay and 16 samples for short delay (the total size of the buffer FIFO is 512 samples for both channel, leaving room for some decimation during sample rate conversion. Anyway, it doesn't help directly with the jitter). Data path is 24 bit wide.
CS8421 doesn't make any refference to a buffer memory for jitter correction... except that the data in buffer will overflow if incoming "changes more than 10%/sec"? It might not use any part of that buffer for jitter reduction... Data path is 32 bit wide.
AD1896 has 64 samples for long delay and 16 samples for short delay (the total size of the buffer FIFO is 512 samples for both channel, leaving room for some decimation during sample rate conversion. Anyway, it doesn't help directly with the jitter). Data path is 24 bit wide.
CS8421 doesn't make any refference to a buffer memory for jitter correction... except that the data in buffer will overflow if incoming "changes more than 10%/sec"? It might not use any part of that buffer for jitter reduction... Data path is 32 bit wide.
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It's a bit OT (my excuses to the OP) but at this point, the only figures I've found about the SRC4192's jitter rejection are some measurements made by Stereophile of the DAC25.2, which uses that chip. According to them "Switching on the oversampling eliminated the data-related sidebands (fig.12) and dropped the measured jitter below the resolution limit of the Miller Analyzer with both S/PDIF and USB data." (see Music Hall dac25.2 D/A processor Measurements | Stereophile.com for details).
End of the OT.
PS: While we're speaking of digital receivers, the SRC4392 is a bit puzzling, once one read this : Musical Fidelity V-DAC D/A processor Measurements | Stereophile.com It's still possible that Musical Fidelity messed up their implementation of the IC wrt spdif inputs.
Just to add more questions to the SRC4192 versus AD1896 jitter rejection mystery, there is this linked report from Benchmark about the relative performance of these two ASRC chips.
Jitter Reduction Using PLL and ASRC Devices | Benchmark Interaction
Jitter Reduction Using PLL and ASRC Devices | Benchmark Interaction
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Found that article: Web Bonus: Audio Semiconductors 2008
Bruno Putzeys and J. Siau from Benchmark once again state their disagreement. At the question to know which asrc they use, they answer:
"Bruno Putzeys: The TI parts. The SRC4192 has an unbeatable ratio estimator, at least for moderate input jitter (for large input jitter the performance jumps from excellent to unacceptable in one go). Wish the filters were up there too though.
John Siau: We use the AD1896 because of its low PLL corner frequency and unsurpassed jitter attenuation. There are some competing SRC designs that fail to attenuate low-frequency jitter.
Ian Dennis: I’ve been wondering recently whether the SRC dragon has finally been slain. The new breed of integrated SRCs are probably plenty good enough, at least in situations where they can be operated with well-behaved clocks. I think that the market-resistance to SRCs is now mostly historical rather than technical. My current favourite is the SRC4192 (I don’t work for TI, by the way)."
Bruno Putzeys and J. Siau from Benchmark once again state their disagreement. At the question to know which asrc they use, they answer:
"Bruno Putzeys: The TI parts. The SRC4192 has an unbeatable ratio estimator, at least for moderate input jitter (for large input jitter the performance jumps from excellent to unacceptable in one go). Wish the filters were up there too though.
John Siau: We use the AD1896 because of its low PLL corner frequency and unsurpassed jitter attenuation. There are some competing SRC designs that fail to attenuate low-frequency jitter.
Ian Dennis: I’ve been wondering recently whether the SRC dragon has finally been slain. The new breed of integrated SRCs are probably plenty good enough, at least in situations where they can be operated with well-behaved clocks. I think that the market-resistance to SRCs is now mostly historical rather than technical. My current favourite is the SRC4192 (I don’t work for TI, by the way)."
Well, they claim to have actually measured that result with their Audio Precision test rig.
Without the 512 word buffer (with 64 word alocated to jitter suppresion), that does exactly nothing. Even AD says that in their datasheet (page 19).
I am just amazed that TI doesn't have implemented the same mechanism in their cip. True is that their refference to that audio buffer is kind of sketchy at the best. But there is a register that is dedicated specially to work with that buffer... Is just bad implemented?
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But it is the rate-estimator block, or more specifically, the digital servo loop which is responsible for the outstanding jitter rejection of the AD1896. Figure 8 on page 20 depicts the digital servo's loop response - which, not so coincidently, is also the jitter transfer mask for the device. Page 19 only speaks of the FIFO with respect to it providing a data buffer for the succeeding signal processing blocks, not for anything related to jitter rejection. Think of it this way, if a FIFO were responsible for the AD1896's jitter rejection then any residual jitter error would still exist in the time domain and not be permanently encoded into the data, as ASRC naysayers love to point out.
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