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Old 14th February 2011, 09:34 PM   #21
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Arrow Jitter is converted into amplitude errors @ reclocking / ASRC

Quote:
Originally Posted by Ken Newton View Post
Tom,

Just to be certain this clear, it's only the residual jitter - that which remains after strong suppression - which ASRC converts to an amplitude error. This conversion of jitter (time-domain) error in to an amplitude (frequency-domain) error occurs with ALL residual jitter sources. With ASRC it occurs just before D/A conversion. With PLLs, FIFO based technologies, etc., it occurs after D/A conversion. Anyone who doubts that timing jitter manifests in the frequency-domain as an amplitude error should ask themselves exactly how FFT based jitter analyzers function.
It's been a good day - I learned something new. I never thought about jitter being converted to amplitude errors when reclocking / ASRC; never thought about the phenomenon.
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Old 14th February 2011, 09:34 PM   #22
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Quote:
Originally Posted by TomHinton View Post
I don't believe AD1896 can operate in Master mode and have 192 KHz out. Other ASRC from TI and AKM can, but to do so, they skimped on the algorithm. AD1896 needs more computation clocks than are available if control clock is used to generate CKOUTs @ 192 KHz. I would think that AD engineers thought it was important enough to keep this implementation complication in order to achieve best sound.
That's correct. In audio-port master mode, you have to run the AD1896's master clock at 256FS. Which, for 192KHz sample rate is around 49MHz. Well beyond what the AD1896 will support at it's MCLK input.
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Old 14th February 2011, 10:44 PM   #23
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Quote:
Originally Posted by TomHinton View Post
Sonic_real_one :

You are mistaken. Look at the data sheet for AD1896. The output clock uses a totally seperate clock which has nothing to do with the data in clock. It can be something like the new Crystek clocks with ~ 1ps jitter.
I am not.
Without a serious buffer memory, either you are locked onto incoming clock (and jitter) or you are locked onto the external clock and you will skip and repeat samples - based on the instantaneous difference between incoming jittery clock and the precise one.
AD1896 USES that buffer memory - the FIFO buffer. It is just kind of small to attenuate low-frequency jitter. 512 words deep for both channels. How long would take for half of that to empty?
Anyway is better than zero

Last edited by SoNic_real_one; 14th February 2011 at 11:09 PM.
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Old 14th February 2011, 11:49 PM   #24
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Quote:
Originally Posted by TomHinton View Post
Does anybody have a high quality divide circuit that introduces low jitter?
If you want divide by 2, one of these ought to do a reasonable job. One of the main sources of jitter in digital logic is ground bounce, so the package size needs to be small to reduce lead inductance.

http://focus.ti.com/lit/ds/symlink/sn74lvc1g80.pdf

Why do you think the word clock is the one that counts? I think DAC chips these days tend to synchronise word clock with MCLK internally.
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Old 15th February 2011, 12:14 AM   #25
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Originally Posted by abraxalito View Post
If you want divide by 2, one of these ought to do a reasonable job. One of the main sources of jitter in digital logic is ground bounce, so the package size needs to be small to reduce lead inductance.

http://focus.ti.com/lit/ds/symlink/sn74lvc1g80.pdf

Why do you think the word clock is the one that counts? I think DAC chips these days tend to synchronise word clock with MCLK internally.
Need to divide by 2 for BCK and by 128 for WDCK / LRCK. Currently using 2 '161s but there must be a better way to optimize the function.

PCM1704 K grade (whose overall implemented performance has not been surpassed) does not use MCK. Output timing is determined by LRCK and that is where jitter will manifest itself. Jitter on other clocks is irrelevant unless it is so severe as to cause datas errors. (Never happens).
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Old 15th February 2011, 12:58 AM   #26
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Originally Posted by TomHinton View Post
I see. There IS real improvement because incoming jitter is suppressed before it's effect is imposed on the output. Of course the 1ps MCK has to be divided to get SCK and WDCK, so jitter goes back up, especially WDCK, which is divided most and also is only one that counts.

Does anybody have a high quality divide circuit that introduces low jitter?
I'm currently dividing MCLK, using 74VHC161 synchronous counters, to derive both BCLK and WDCK for an AD1896 based DAC of my own design. It's hard to know what jitter we are, or are not, ridding ourselves without the proper test equipment. Although, I have found certain improvements to be immediately audible. One of the tweaks I've found to make a big improvement is to damp all digital signal lines with series placed resistors of significant values (on the order of 100 to 470 ohms, exact values depend). There is much overshoot and undershoot (ringing) evident on such undamped signal lines that is visible with a good scope. My Tektronix DSO had read 4.5 Volts pk-pk on one particular line driven by a 3.3 Volt supply chip! I dampened it with 100 ohms. The improvement (a more at ease sound quality) was immediately audible.

One other comment, regarding the PCM1704. It seems that the critical clock signal for the PCM1704 may not be WDCK, but rather BCLK. I know, this is controversial, but it appears that while WDCK is used to latch each sample word in to the input register BCLK may be used to actually trigger the conversion. Such is vaguely suggested, but not explicitly stated, on page 7 of the datasheet under, "Stopped Clock Operation". I would give as much care to the handling of BCLK as to WDCK, just to be safe.
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Old 15th February 2011, 01:25 AM   #27
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Quote:
Originally Posted by TomHinton View Post
PCM1704 K grade (whose overall implemented performance has not been surpassed) does not use MCK.
Performance here meaning something other than measurements? Yes, I agree there's no MCK just BCK on PCM1704. Figure 1, page 7 of the datasheet shows data updating on the rising edge of BCK.
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Old 15th February 2011, 01:32 AM   #28
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I have seen using Rs in all the signal lines to-from all the ICs before (some as high as 2K), and set up a proto board to have provision for them. Currently, I have 100 ohms out of the DF1706 to the PCM1704s ( AD1896 @ 192 out > DF1706 @ 4x @ 768 out > PCM1704. ) I could not hear any difference with/without them. I'm using AC161s, maybe I should try VHC161? Why would VHC be better choice?

I was not aware if the inference contained in "stopped clock operation". Thanks. Anyway, low jitter on all CKs would be good design practice.

I could definitely hear an impoivement when I installed one of the Crystek 1ps jitter clocks.

Last edited by TomHinton; 15th February 2011 at 01:51 AM.
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Old 15th February 2011, 12:10 PM   #29
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Hi Tom,

HC series are notoriously noisy. VHC series are supposed to be more quiet, although I haven't experimentally verified this. Perhaps, the 74HCs were too noisy to enable you to hear the improvement from those damping resistors. Give the VHCs a try and let us know.

Right page, wrong section of the PCM1704 datasheet. Following, is the quote I was alluding to, under "Basic Operation" on page 7: "The serial-to-parallel data transfer to the DAC occurs on the falling edge of WCLK." Just as we would expect. Then this: "The change in the output of the DAC occurs at the rising edge of the 2nd BCLK after the falling edge of WCLK." I'd say that last sentence rather clearly states that the instant of conversion is determined by the rising edge of BCLK - two whole cycles after the edge of WCLK .
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Last edited by Ken Newton; 15th February 2011 at 12:17 PM.
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Old 15th February 2011, 06:04 PM   #30
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Actually I had skimmed over this part of the data sheet missing the full implications. Seems like this is good news, because BCK is less likely to have excess jitter, only being divided down by 2.
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