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Old 14th February 2011, 06:50 PM   #11
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Default Reclocking

In most RX chips, the crystal clock is only used to compare PLL to a referencs so that incoming rate can be displayed, or supply a clock if no digital in for the PLL. The incoming rate will never be exactly sunchronous with a crystal, so if reclocking occurs, some samples will have to be repeated or skipped. Unless SRC is implemented. Does anyone know if SRC is implemented on WM8805 RX chip, and does it outperforms AD1896?

Last edited by TomHinton; 14th February 2011 at 07:11 PM.
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Old 14th February 2011, 08:23 PM   #12
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Even a SRC doesn't eliminate the jitter, the output will be locked to the input signal via a PLL and a programmable divider.
The only way to eliminate the jitter (without skipping or repeating audio data) is to use a buffer memory, fill it half way with data - clocked with the incomming clock and read it with a stable local Xtall clock.
From what I know none of the simple receivers off-the-shelf are doing that.
The only way I have seen it done is with a DSP that usually uses some kind of DMA and memory to achieve that buffering.
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Old 14th February 2011, 08:52 PM   #13
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The most important difference between DIR chips is not their intrinsic jitter specifications. Intrinsic jitter can be thought of as the jitter which would still remain even if the incoming signal contained absolutely no jitter. As has been noted, many DIRs show intrinsic jitter figures of 50ps. The more interesting specification is their jitter transfer mask profiles. The transfer mask is a curve telling how much and at what frequencies recieved signal jitter is suppressed. One of the big problems is that not all datasheets show this profile. This absence is particularly annoying with the DIR9001 because of it's hyping of SpAct. jitter reduction technology.

As far as ASRC is concerned, they are capable of tremendous jitter suppression, particularly so for the AD1896. Just compare the transfer mask profile of the AD1896 to that of any DIR chip, or to that of the CS2300. Before anyone informs me otherwise, the truth that ASRC does convert residual jitter to a amplitude error does nothing to diminish the effectiveness of this technology. Here's a secret, all residual jitter, whatever it's source, is converted to an amplitude error by the DAC chip.
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Old 14th February 2011, 08:57 PM   #14
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Arrow Output clock for SRC chips is not related to input clock

Sonic_real_one :

You are mistaken. Look at the data sheet for AD1896. The output clock uses a totally seperate clock which has nothing to do with the data in clock. It can be something like the new Crystek clocks with ~ 1ps jitter.

Last edited by TomHinton; 14th February 2011 at 09:00 PM.
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Old 14th February 2011, 09:02 PM   #15
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Originally Posted by Ken Newton View Post
As far as ASRC is concerned, they are capable of tremendous jitter suppression, particularly so for the AD1896. Just compare the transfer mask profile of the AD1896 to that of any DIR chip, or to that of the CS2300. Before anyone informs me otherwise, the truth that ASRC does convert residual jitter to a amplitude error does nothing to diminish the effectiveness of this technology. Here's a secret, all residual jitter, whatever it's source, is converted to an amplitude error by the DAC chip.
If SRC passes incoming jitter through as amplitude errors, is there any real improvement by reclocking?
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Old 14th February 2011, 09:06 PM   #16
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Originally Posted by TomHinton View Post
You are mistaken. Look at the data sheet for AD1896. The output clock uses a totally seperate clock which has nothing to do with the data in clock. It can be something like the new Crystek clocks with ~ 1ps jitter.
That's right, Tom. ASRC enables two independent clock domains. The jitter at the output side of an ASRC chip will be determined by two factors. The residual jitter from the input side clock after strong suppression by the ASRC, and the intrinsic jitter of the output side clock generator.
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Old 14th February 2011, 09:15 PM   #17
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Originally Posted by TomHinton View Post
If SRC passes incoming jitter through as amplitude errors, is there any real improvement by reclocking?
It depends on how you are generating the output side clock. If you are using the ASRC chip in master mode, where the ASRC itself is generating the word-clock and bit-clock signals going to the DAC, then, yes, you will want to synchronously re-clock those signals from a low jitter clock source. Which should be the same source serving as the master clock for the ASRC chip. If you instead are using the ASRC in slave mode, where you are dividing down a low jitter local clock source to generate word-clock and bit-clock, then the divider itself inherently serves to "re-clock" those signals for lowest intrinsic output side jitter.
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Last edited by Ken Newton; 14th February 2011 at 09:18 PM.
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Old 14th February 2011, 09:20 PM   #18
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Originally Posted by Ken Newton View Post
That's right, Tom. ASRC enables two independent clock domains. The jitter at the output side of an ASRC chip will be determined by two factors. The residual jitter from the input side clock after strong suppression by the ASRC, and the intrinsic jitter of the output side clock generator.
I see. There IS real improvement because incoming jitter is suppressed before it's effect is imposed on the output. Of course the 1ps MCK has to be divided to get SCK and WDCK, so jitter goes back up, especially WDCK, which is divided most and also is only one that counts.

Does anybody have a high quality divide circuit that introduces low jitter?
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Old 14th February 2011, 09:25 PM   #19
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Originally Posted by Ken Newton View Post
It depends on how you are generating the output side clock. If you are using the ASRC chip in master mode, where the ASRC itself is generating the word-clock and bit-clock signals going to the DAC, then, yes, you will want to synchronously re-clock those signals from a low jitter clock source. Which should be the same source serving as the master clock for the ASRC chip. If you instead are using the ASRC in slave mode, where you are dividing down a low jitter local clock source to generate word-clock and bit-clock, then the divider itself inherently serves to "re-clock" those signals for lowest intrinsic output side jitter.
I don't believe AD1896 can operate in Master mode and have 192 KHz out. Other ASRC from TI and AKM can, but to do so, they skimped on the algorithm. AD1896 needs more computation clocks than are available if control clock is used to generate CKOUTs @ 192 KHz. I would think that AD engineers thought it was important enough to keep this implementation complication in order to achieve best sound.
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Old 14th February 2011, 09:27 PM   #20
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Tom,

Just to be certain this is clear, it's only the residual jitter - that which remains after strong suppression - which ASRC converts to an amplitude error. This conversion of jitter (time-domain) error in to an amplitude (frequency-domain) error occurs with ALL residual jitter sources. With ASRC it occurs just before D/A conversion. With PLLs, FIFO based technologies, etc., it occurs after D/A conversion. Anyone who doubts that timing jitter manifests in the frequency-domain as an amplitude error should ask themselves exactly how FFT based jitter analyzers function.
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Last edited by Ken Newton; 14th February 2011 at 09:38 PM.
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