Custom Low Jitter MCLK for DAC's

[ljfont]

Seen a few products using a the crystek crystal featuring:
1. Low Jitter < 1pSec
2. Fundamental & 3rd Overtone Crystal Design

Question: what is the best known frequency division circuit, specifically geared toward low jitter? Flip flops or PLL's.

Looking for master clock solutions, also it seems like some DAC's have a built in PLL.

[singa]

Originally Posted by ljfont

Seen a few products using a the crystek crystal featuring:
1. Low Jitter < 1pSec
2. Fundamental & 3rd Overtone Crystal Design

Question: what is the best known frequency division circuit, specifically geared toward low jitter? Flip flops or PLL's.

Looking for master clock solutions, also it seems like some DAC's have a built in PLL.

Hi,
This question is like a loaded gun.I would not dare to answer.The best way to put it is that to find your solution,you need to understand how
digital circuits work, that is how a digital oscillator work and what is jitter.

What is noise?.Next is the relationship of inherent/circuit noise to jitter.How does a PLL work,what are it's building blocks.How do you clean up a noisy signal.Then finally you look
at the big picture which is your electrical circuit and why LRC (inductance,resistance and capacitance) affects circuit behaviour.After this you will have an apreciation of the difficulty of achieving timing accuracy and drift in an electrical circuit.Is absolute timing accuracy important or relative accuracy?

What is available commercially cannot meet your needs? This imply
you should know the problems and the ways or method to solve them.
Most important,does it make a difference in performance sonically?
Singa

[ljfont]

There is a lot to be understood about many things. I'm just looking for some circuit ideas so I can build and implement a MCLK. Most DAC circuits that I see rely on sample rate converters to do the trick. Some seem to have some PLL type or other scheme built in to the DAC to reduce jitter. I've read somewhere that some flip flop circuit (ECL) based stuff was good for this kind of thing.

Lots of different techniques that manufacturers seem to use. I'm just looking for an alternative MCLK to experiment with in my system.

[singa]

Originally Posted by ljfont

There is a lot to be understood about many things. I'm just looking for some circuit ideas so I can build and implement a MCLK. Most DAC circuits that I see rely on sample rate converters to do the trick. Some seem to have some PLL type or other scheme built in to the DAC to reduce jitter. I've read somewhere that some flip flop circuit (ECL) based stuff was good for this kind of thing.

Lots of different techniques that manufacturers seem to use. I'm just looking for an alternative MCLK to experiment with in my system.

Hi, If you are hoping that someone will post a circuit with that extra signal
conditioning features that standard clock offerings on the market do not have
then you are not being realistic.If there were all of us would not be asking
similar questions.

It is a black art that normal people would not have the knowledge or
experience nor the resources.If you are willing to investigate the art of PLL design you may reap rewards that people are too lazy to do.What I can suggest is that you visit semiconductor websites and troll the application notes and related info like web seminars there are tons of info that is useful
for understanding the "secrets" of electronics.National Semiconductor is one
such site.Just look for timing solutions or PLL. Good luck.
Singa

[MatchASM]

Originally Posted by ljfont

Question: what is the best known frequency division circuit, specifically geared toward low jitter?

What is the division ratio?

You might anyhow be interested in the concept of "reclocking".

Unless your division ratio is exactly 2, reclocking eliminates the accumulated jitter added by a divider chain.

It is kind of black magic (I have a couple of patents pending in this field). For a beginner, I recommend you try getting hold of the IEEE papers on 2/3-divider cells by Cicero Vaucher and friends. They do reclocking, give you a fairly arbitrary divider ratio and can be built in ECL.

A PLL is preferably avoided, unless you aim for a non-integer division ratio.

--
Greetz,
MatchASM

[singa]

A master has deigned to reply.Thank you MatchASm.

ljfont ,you have been given a hint.Thank your lucky stars.Although you have
not been handed a silver platter, the rest is up to you.Earn your stripes as
they say. If you should succeed and you are kind enough then share it
with us?