how to detect external clock's frequency

tommy303 · 7th December 2010, 01:38 PM

hey there,

I'm working on an audio interface which should be capable of synchronizing to an external word clock signal (sample rate). I'm just wondering how that's done, because: everything I get from outside, is the word clock signal. the master clock frequency for the ICs is of course many times (256fs @ 44.1) higher. where do I get the master clock signal from? maybe by synchronizing an internal clock generator with the external signal? I think about using the CS2000 by cirrus, but I can't find a way, how to synchronize to an external word clock signal with this IC. maybe there's a better way/IC?

so, in master mode everything's fine. I can produce the 11.2896 as well as the 12.288 MHz with the CS2000 and divide down to the needed frequencies for I2C and of course the sample rate itself, but what if I want to use an external word clock signal (44.1, 48, 96 and 192)? that's basically the question.

thanks a lot in advance.

best regards
tommy

rfbrw · 7th December 2010, 07:41 PM

A PLL/VCXO combination is used.

tommy303 · 7th December 2010, 07:49 PM

you mean something like the CDCE913 from TI? or could you give an example IC please?

rfbrw · 7th December 2010, 08:19 PM

A combination of devices are used as opposed to a single chip. The Pass D1 schematic and the PMD100 demoboard schematic are two good examples.

tommy303 · 8th December 2010, 06:29 AM

ok, thanks. I'm gonna take a look at. I also found your answer to more or less this question on diyhifi.org. this helps a lot.

cheers
tommy

7th December 2010, 01:38 PM	#1
tommy303 diyAudio Member Join Date: Oct 2010 Location: Duisburg, Germany	how to detect external clock's frequency hey there, I'm working on an audio interface which should be capable of synchronizing to an external word clock signal (sample rate). I'm just wondering how that's done, because: everything I get from outside, is the word clock signal. the master clock frequency for the ICs is of course many times (256fs @ 44.1) higher. where do I get the master clock signal from? maybe by synchronizing an internal clock generator with the external signal? I think about using the CS2000 by cirrus, but I can't find a way, how to synchronize to an external word clock signal with this IC. maybe there's a better way/IC? so, in master mode everything's fine. I can produce the 11.2896 as well as the 12.288 MHz with the CS2000 and divide down to the needed frequencies for I2C and of course the sample rate itself, but what if I want to use an external word clock signal (44.1, 48, 96 and 192)? that's basically the question. thanks a lot in advance. best regards tommy

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7th December 2010, 07:41 PM	#2
rfbrw diyAudio Member Join Date: Oct 2001 Location: .	A PLL/VCXO combination is used.

7th December 2010, 07:49 PM	#3
tommy303 diyAudio Member Join Date: Oct 2010 Location: Duisburg, Germany	you mean something like the CDCE913 from TI? or could you give an example IC please?

7th December 2010, 08:19 PM	#4
rfbrw diyAudio Member Join Date: Oct 2001 Location: .	A combination of devices are used as opposed to a single chip. The Pass D1 schematic and the PMD100 demoboard schematic are two good examples.

8th December 2010, 06:29 AM	#5
tommy303 diyAudio Member Join Date: Oct 2010 Location: Duisburg, Germany	ok, thanks. I'm gonna take a look at. I also found your answer to more or less this question on diyhifi.org. this helps a lot. cheers tommy