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Old 21st September 2010, 08:26 AM   #11
Calvin is offline Calvin  Germany
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Hi,

distortion- and noisewise You wont give up much. The PCM1794As distortions are on par or even below the datasheets values in SE mode.
With noise figures of less than -110dB it would be hard to preserve such a low value through the analog output stages.
Cancelation of even harmonics will miss out in SE mode, but on the other hand this means a more natural spectrum of harmonics.
Id terminate the 2nd unused DAC-output with an equal stage or at least with a similar impedance.
btw. the I-values in the Sim are not identical to the PCM1794As values (-6.2mA+-3.9mA, or in Mono-mode: -12.4mA+-7.8mA). The centre currents need to be sinked by dedicated current sinks or the circuit needs redesign.
What is the purpose of the I3 spanning the JFETs sources?
As designed, check the power losses of the JFETs. With +-30V I doubt they will survive the burning

jauu
Calvin

ps: ...and yes an old NE5534 or other OP-amps will do the I/V-conversion job too....but will they sound well? My ears tell different.....very much different
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Old 21st September 2010, 02:44 PM   #12
DougL is offline DougL  United States
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Calvin,
Thanks for the reply.
Quote:
distortion- and noisewise You wont give up much
Good to hear.
Quote:
Id terminate the 2nd unused DAC-output with an equal stage or at least with a similar impedance
Sounds good. I think I will terminate with an equal stage so I can try both SE and Balanced.
Quote:
The centre currents need to be sinked by dedicated current sinks or the circuit needs redesign
Won't the center current just produce a DC offset on the jfets that will be handled by the coupling caps? I can see for transformer out, a current imbalance might be very bad.

Doug
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Old 24th September 2010, 04:45 PM   #13
Calvin is offline Calvin  Germany
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Hi,

the idle currrents in the positive branch will differ from that in the negative branch. In the best case this just means a DC-offset without generating greater probs, but in any case it means, that this complementary symmetrical circuit doesnt work symmetrical any more and one of the branches could even be driven into clipping (the DACs centre current runs through the negative branch into the negative supply). Besides the fact that N- and P-type JFETs are not very complementary in first place, do different currents mean different working points, different temperature, etc.
The SK170/SJ74 come in TO92 casings and are rather lowcurrrent devices with less than 20mA Idss and less than 400mW heat power loss. If You run them on 30V supplies with sufficiently large idle currents.....well ..... the joy probabely wont last long....but the heat is...bom bom bom....On
If You want to deal with the DACs idle current within the circuitry itself, You are probabely much better off with a SE- or asymmetrical design, e.g a simple SE-grounded base circuit like the Jocko. If You want to stay -for what reasons ever- with a complementary symmetrical circuit then better choose a dedicated current sink for the DACs centre current, so that the I/V converter is fed only with a smaller and DC-centered input current.

jauu
Calvin
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Old 11th October 2010, 06:51 PM   #14
DougL is offline DougL  United States
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Calvin,
I have been doing research. As far as I can tell from the data sheet in Fig 31, both Analog outputs have a -6.2 mA current at idle, inversely varying from -10.1 mA to -2.3 mA.
So a 6.2 V CSS to the negatives supply would take care of the center current.
I do not have any feel if the 3.2 mA current is too much for the jfet with a Idd of 10 mA.
Would you recommend I double up the jfets or try them single first.

Doug
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