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-   -   DAC chip selection + I2S jitter questions (http://www.diyaudio.com/forums/digital-line-level/170844-dac-chip-selection-i2s-jitter-questions.html)

drwho9437 26th July 2010 08:30 AM

DAC chip selection + I2S jitter questions
 
I think I must have hit only the preview button oh boy I get to write this again!...


I am working on an audio project and am in the early stages of part selection.

There seem to be many choices for DACs out there.

A lot of designs here use TDA1541A I assume that is in large measure because it is a hole through part making it easier to work with.

I will have a large number of SMD parts anyway. Some other DACs that seem to be common are ES9018, WM8741/WM8740, PCM1794A, AD185, and some other AD part.

So my first question is what are the opinions on these, what others are worth looking at, what do you look at when making selections for DAC (other than the obvious specs (SNR, DR, THD)).

I was leaning toward WM8740 for simplicity and cost, although cost really isn't a big deal, the rest of the system cost will be large dwarfing the DAC...


Next, I read somewhere about jitter on the input stream to the DAC being passed to the output. I believe this was in the context of some PCM bitstream from a USB codec.

Now to me that doesn't make much sense. Jitter is effectively phase noise, but if the jitter is on the digital stream surely if the reference clock for the DAC is low jitter and nice then the output should be clean?

In my project there will be a I2S stream that may well be very nasty in terms of phase noise (jitter). Now if I were making a DAC it would have some FIFO buffer in it, that would read the data stream then given the settings of the bitstream it would output the bits reference to its clock on the analog out. Thus any jitter in the I2S stream would not be relevant as long average clock was correct within the tolerance of the serial interface.

So my question is, am I wrong? Would jitter on the I2S stream be passed through assuming a low jitter reference on the DAC?

SoNic_real_one 26th July 2010 01:31 PM

FIFO buffers don't work . Only if they are very big (like minutes big) and you pre-buffer a LOT.
Otherwise, a small difference in the two frequencies will add up constantly and lead to missed or added data.

That's why there is only one reference - usually the one in the transport. It can be in the DAC (if it is separated). But I2S is safer for jitter (compared with SPDIF or other), since the clocks are separated from data.
If you want jitter reduction, the options are a re-clocking chip (SampleRateConverter) or a dedicated DSP or dedicated software for a specific DSP.
Some DAC's are more or less immune to jitter, based on the internal architecture.

drwho9437 26th July 2010 01:50 PM

gotcha, I guess that makes sense I was presuming they both has a true freq and phase noise I hadn't considered crystal tolerances.


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