cs8416 + pcm56p

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It's to keep the clocks synchronously. The clock for the lower DAC is stopped certain periods of the Latch, hence the name "stopped clock" method.

Anyway the method with simply inverting the latch for 1 channel sounded slightly better. This was tried with the AD1865 though.

74HC08 is an AND gate, doesn't make sense that the signal and +5vDC are being input into the gate?
 
I2s to AD1856, I think will work for PCM56, see attached.
 

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Eureka

Guys I've been messing with this for a while now and could never get it to work
(single inverter) I was was getting a lot of noise in the non inverted channel.
However after some more fiddling last night I had success ,initial listening sounds promising:)
I'm using CS8414 74VHC04 PCM56P
See schema below.
 

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Bernhard you have my utmost attention and respect but what do you mean exactly by problems with timing? This sounds awesome the way it is, eg no TDA and no op amps ,:boggled:
PS data and clock wires are less than 15mm.

Longer wires can cause trouble but if you have no problems, all ok :)

Film caps for decoupling on all power supply pins would be good.

You can try this integrated analog filter: passive I/V + 24 dB lowpass from 20 khz + hf rolloff compensation.
It results in equivalent of 100 ohm passive I/V so you may need some post amplification.
Connect nothing else to Iout.


audiofilter.jpg
 
2 X5V

Longer wires can cause trouble but if you have no problems, all ok :)

Film caps for decoupling on all power supply pins would be good.

You can try this integrated analog filter: passive I/V + 24 dB lowpass from 20 khz + hf rolloff compensation.
It results in equivalent of 100 ohm passive I/V so you may need some post amplification.
Connect nothing else to Iout.


audiofilter.jpg

Chips are all decoupled with Millitary grade 100nF glass passivated caps at pins
Only 2 X 5V rails and this little baby is kicking some major ***.:sing:
 
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