Hi,
I am trying to parallel 8 or 9 pieces of TDA1541A S1 dacs in non-os mode. Unfortunately i could not find the formula for calculation of bit error reducing by using parallel dacs (2x,4x,8x, so on) and also about reducing of the distortion. Is there any meaning of using 9 pieces instead of 8? Sorry for my bad English.
Thanks a lot!
http://stereomecmuasi.com/forum/viewtopic.php?f=46&t=1554&p=15441#p15441
I am trying to parallel 8 or 9 pieces of TDA1541A S1 dacs in non-os mode. Unfortunately i could not find the formula for calculation of bit error reducing by using parallel dacs (2x,4x,8x, so on) and also about reducing of the distortion. Is there any meaning of using 9 pieces instead of 8? Sorry for my bad English.
Thanks a lot!
http://stereomecmuasi.com/forum/viewtopic.php?f=46&t=1554&p=15441#p15441
Paralleling of 2 DAC's means doubling of the output current - that is 6dB.
The noise and distortion (TDH+N), because there are not statistically corellated between chips, will increase only with 3dB (some fancy math is involved here).
So doubling the output adds 6-3= 3dB to the current TDH+N ratio.
2 DAC -> 3dB
4 DAC -> 6dB
8 DAC -> 9dB
Increasing the current TDH+N means nothing if you cannot translate it into voltage with the same TDH+N. The I/V stage has a noise floor (and a distortion level), even if you are using a resistor, at room temperature will generate a noise.
So, at some point adding DAC's will improve nothing in the global S/N because you are already below I/V stage noise floor.
The noise and distortion (TDH+N), because there are not statistically corellated between chips, will increase only with 3dB (some fancy math is involved here).
So doubling the output adds 6-3= 3dB to the current TDH+N ratio.
2 DAC -> 3dB
4 DAC -> 6dB
8 DAC -> 9dB
Increasing the current TDH+N means nothing if you cannot translate it into voltage with the same TDH+N. The I/V stage has a noise floor (and a distortion level), even if you are using a resistor, at room temperature will generate a noise.
So, at some point adding DAC's will improve nothing in the global S/N because you are already below I/V stage noise floor.
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Hi,
First, the TDA1541A has a Typical SNR at digital zero of 110dB(A).
Secondly, the TDA1541A is typically rated as -102dB(A) THD & N at -60dB signal.
Arguably, these measurements come from a 176.4KHz sample rate signal, but one without noise-shaping etc.
As the absolute maximum dynamic range (peak-peak) of 16 Bit audio is 93.7dB the TDA1541A is basically so close to or well past the limits for 16-Bit audio signals that no material improvement is possible by using multiple devices.
However, this performance is only attained if the DEM Clock is synchronised to the digital data and the power-supply design is of the highest quality. Rather than paralleling ton's of TDA1541A, I would suggest optimally implementing a single one as the better route to get the best possible sound quality from the TDA1541.
Of course, paralleling devices still induces changes in sound quality. I personally find the effects of paralleling DAC's in an otherwise fully optimised system not particularly to my liking.
Ciao T
First, the TDA1541A has a Typical SNR at digital zero of 110dB(A).
Secondly, the TDA1541A is typically rated as -102dB(A) THD & N at -60dB signal.
Arguably, these measurements come from a 176.4KHz sample rate signal, but one without noise-shaping etc.
As the absolute maximum dynamic range (peak-peak) of 16 Bit audio is 93.7dB the TDA1541A is basically so close to or well past the limits for 16-Bit audio signals that no material improvement is possible by using multiple devices.
However, this performance is only attained if the DEM Clock is synchronised to the digital data and the power-supply design is of the highest quality. Rather than paralleling ton's of TDA1541A, I would suggest optimally implementing a single one as the better route to get the best possible sound quality from the TDA1541.
Of course, paralleling devices still induces changes in sound quality. I personally find the effects of paralleling DAC's in an otherwise fully optimised system not particularly to my liking.
Ciao T
My take on the issue is a linearity error may be a plus or minus error.... that adding more DACs should average the error rate to lower value...
For example the S chip provide a .5 LSB error rate. plus or minus... so one chip may be -.5 LSB and another may be +.5 lsb at a given value. But additively between the two of them.... no error a the same value. The more you average, the lower the error rate. Even if the spec is only a positive error rate only, the result is the same improvement in linearity averaged over the full range.
But in my mind the real value of multi TDA1541s came with implementing EC-Design's linear interpolation design....that made the whole multi-dac results over the top for me.
jk
For example the S chip provide a .5 LSB error rate. plus or minus... so one chip may be -.5 LSB and another may be +.5 lsb at a given value. But additively between the two of them.... no error a the same value. The more you average, the lower the error rate. Even if the spec is only a positive error rate only, the result is the same improvement in linearity averaged over the full range.
But in my mind the real value of multi TDA1541s came with implementing EC-Design's linear interpolation design....that made the whole multi-dac results over the top for me.
jk
Hi,
Hmmm, I have measured the TDA1541A (also S1 & S2) on an AP Two. Have you?
I'd disagree with "urban legend".
Ciao T
Hmmm, I have measured the TDA1541A (also S1 & S2) on an AP Two. Have you?
I'd disagree with "urban legend".
Ciao T
Hi,
Yes. Note that I quoted SNR at Bipolar Zero, not full scale (page 7 in the file you link), it is 110dB.
Also note that THD & N at -60dB is typical -42dB.
All DAC's (even the latest ones) degrade considerably near full scale, this behaviour however is not indicative of the behaviour at low levels, which is where we are generally interested in.
Modern day dynamic range measurements are often taken with -60dBfs signals, with these the TDA1541A shows an excellent performance for a 16 Bit chip with good sample-to-sample consistency (we employ it in series production).
The bottom line is that even with your set of numbers the TDA1541A is sufficiently high in performance that paralleling does not improve performance with a real signal.
Ciao T
Yes. Note that I quoted SNR at Bipolar Zero, not full scale (page 7 in the file you link), it is 110dB.
Also note that THD & N at -60dB is typical -42dB.
All DAC's (even the latest ones) degrade considerably near full scale, this behaviour however is not indicative of the behaviour at low levels, which is where we are generally interested in.
Modern day dynamic range measurements are often taken with -60dBfs signals, with these the TDA1541A shows an excellent performance for a 16 Bit chip with good sample-to-sample consistency (we employ it in series production).
The bottom line is that even with your set of numbers the TDA1541A is sufficiently high in performance that paralleling does not improve performance with a real signal.
Ciao T
Hi,
Well, even two will not improve SNR/DNR in any appreciable way.
I can see reasons however to parallel many TDA1541A.
For example, unless I inject an offset current the AC voltage on the TDA1541's output should be kept under 50mV (100mV with offset current).
If I want a purely passive output stage (with a transformer) this means I need 1:40 Stepup to get 2V RMS out. By going bridged (balanced) with the DAC's I can reduce the ratio to 1:20.
What it means is that my current voltage resitor at the output of the transformer must be 400 to 1600 times the value of the IV resistor at the DAC, or if I place a low value I/V resistor at the DAC it's resistance is multiplied by the above ratio.
If I have a single TDA1541 with 50mV and 1:40 Steup my output impedance is over 50 KOhm. Now that is a BIT much and a 50K secondary Transformer is not easily wound.
If I parallel (for arguments sake) 16pcs TDA1541A I get around 3K output impedance, still high but quite usable. So I can really concoct a valid application for 64 parallel TDA1541A to get me under 1K output impedance and a fully passive output. Again, not that I'd really recommend building such a monster or that I claim any particular advantages.
Even though with 64 pcs of TDA1541A we could do some interesting resolution enhancement schemes to get up to 22 Bit real resolution (use a nice FPGA to assign the bits from 17 to 22 to the various DAC groups and maybe use additional 'DAC DEM' as well) in 1Fs mode with -128dBfs SNR at bipolar zero. Even 16 pcs could give a true 20Bit with -122dBfs SNR at bipolar zero... And I always could buffer the output with a J-Fet buffer... ;-)
Ciao T
Well, even two will not improve SNR/DNR in any appreciable way.
I can see reasons however to parallel many TDA1541A.
For example, unless I inject an offset current the AC voltage on the TDA1541's output should be kept under 50mV (100mV with offset current).
If I want a purely passive output stage (with a transformer) this means I need 1:40 Stepup to get 2V RMS out. By going bridged (balanced) with the DAC's I can reduce the ratio to 1:20.
What it means is that my current voltage resitor at the output of the transformer must be 400 to 1600 times the value of the IV resistor at the DAC, or if I place a low value I/V resistor at the DAC it's resistance is multiplied by the above ratio.
If I have a single TDA1541 with 50mV and 1:40 Steup my output impedance is over 50 KOhm. Now that is a BIT much and a 50K secondary Transformer is not easily wound.
If I parallel (for arguments sake) 16pcs TDA1541A I get around 3K output impedance, still high but quite usable. So I can really concoct a valid application for 64 parallel TDA1541A to get me under 1K output impedance and a fully passive output. Again, not that I'd really recommend building such a monster or that I claim any particular advantages.
Even though with 64 pcs of TDA1541A we could do some interesting resolution enhancement schemes to get up to 22 Bit real resolution (use a nice FPGA to assign the bits from 17 to 22 to the various DAC groups and maybe use additional 'DAC DEM' as well) in 1Fs mode with -128dBfs SNR at bipolar zero. Even 16 pcs could give a true 20Bit with -122dBfs SNR at bipolar zero... And I always could buffer the output with a J-Fet buffer... ;-)
Ciao T
8XTDA1541A S1 4+4 Monoural NOS DAC
I have made the revision on board. Now, i am using one big board. Another change is on circuit design; four dacs will work for left channel, the other four will work for the right channel. In my opinion, this monoural design will prevent any crosstalk, will ensure better stereo imaging, better channel seperation, better focus. I have already listened one channel, sounding great.
I have made the revision on board. Now, i am using one big board. Another change is on circuit design; four dacs will work for left channel, the other four will work for the right channel. In my opinion, this monoural design will prevent any crosstalk, will ensure better stereo imaging, better channel seperation, better focus. I have already listened one channel, sounding great.
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An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
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Well... I don't know if is correct.
You tied toghether all the pins 17? The internal waveform must be crazy...
http://www.audiofaidate.org/uploaded/andypairo/HtP Dem Description.pdf
You tied toghether all the pins 17? The internal waveform must be crazy...
http://www.audiofaidate.org/uploaded/andypairo/HtP Dem Description.pdf
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