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Old 23rd February 2010, 09:41 PM   #1
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Smile My Complete Solution DAC, RFC

ok, after weeks of reading through the forums here and weeks of hacking through spice, schematic capture and breadboards, i think i've come up with a pretty good start towards a complete solution DAC. i've attached the schematic.

details:

input:
the input section of the DAC uses a PLL-mode DIR9001 with the garden variety TORX147 TOSLINK receiver. i went with TOSLINK because my PC has no coaxial output. the DIR outputs 24-bit data, and all digital elements in the chain following the DIR use the same resolution.

asrc:
the asrc is a SRC4193 (SPI-controlled) that is clocked by a (relatively) low-jitter XO at 24.576MHz. from the front panel, resampling may be set to three modes: OFF (bypass), 48kHz (CLKI/512), and 96kHz (CLKI/256). the ASRC automatically mutes the audio stream when it exists in the non-ready state.

digital interpolation filter:
more boilerplate, really. the DF1704 is used to split the stereo data into left- and right-channel data streams for the downstream DACs, using a slow-rolloff filter.

digital-to-analog converters:
and more boilerplate, at least as far as the schematic goes. two PCM1704U-Ks operating in 24-bit, non-inverting mode => single-ended outputs.

iv converters:
the i/v converters are discrete mosfet converters, essentially modified NP D1 stages. spice shows 0.0055% THD at 1.5mApp@1kHz input, 4Vpp output. the frequency response of the circuit is close to 2Hz-50kHz, -0.1dB. loading the output transistor with a constant-current sink helps both THD and frequency response.

motherboard:
two momentary pushbutton switches, one for power and one for resampling mode selection. one power led, one led to indicate if resampling is enabled, two leds to indicate resample rate (if enabled), and one led to indicate PLL lock/unlock. (the DIR sends its ERROR signal to the micro for this purpose.) the micro also controls relays which switch the power to the digital electronics. during the "off" state, the i/v converters are still powered to keep them warm and stable.

power supplies:
the raw power supplies are essentially garden variety, with the addition of mains filters and common-mode chokes to limit HF noise. amveco dual toroids are used throughout. rectifier diodes are bypassed. the +/-5Vdc and +3.3Vdc supplies are switched by omron G2RL power relays.

i/v converter regulator:
this is a dual-rail salas v1 shunt regulator, where the JFET has been changed to a current-regulating diode (4.7mA). under load, the positive rail sources a constant current of 175mA with 50mA into the shunt. the negative rail sources a constant current of 85mA with 55mA into the shunt.

low(er)-voltage regulators:
the logic voltage regulators are salas shunts just like the i/v converter regulator, but they all output 12V. they're followed immediately by TL431 shunt regulators, which regulate that voltage down to the proper value, which will be adjustable by trimpots. all mosfet shunts are sinking at least 20mA under load. (as per simulations)

i realize 16 pages is alot to swallow, but given the fact that i've been buried in the work for weeks, i'm sure i've made mistakes or passed up better options... this is my first attempt at a dac circuit, so i'd really like to know what you think, so, questions, comments, sniiiide remarks?

thanks!
~ brad.
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Old 24th February 2010, 12:57 AM   #2
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well, i do have one specific question, so far: given the fact that the filter and DACs are at 8X oversampling is there a cutoff high-frequency i need to fix into the I/V converters, or is there no significant HF noise when oversampling?

thanks,
~ brad.
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Old 24th February 2010, 04:45 AM   #3
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If you wish to bypass the sample rate convert, the input sample frequency must match the output. This means you need two clocks: one for the 44.1 family and one for the 48K family. With the clock you specified, you will not be able to bypass the asrc for 44.1K material.
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Old 24th February 2010, 07:46 AM   #4
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What input sample rates are you proposing to accept? The 1704 will go up to only 96k with the DF1704.

Why select the slow roll off in the DF1704? Its performance looks 2-3bits poorer in stop band rejection than the normal setting.

Oh, and while I'm asking questions... given that you're concerned about RF ingression from the mains, why toroidals?

Last edited by abraxalito; 24th February 2010 at 08:12 AM. Reason: added a further question
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Old 24th February 2010, 01:17 PM   #5
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Quote:
Originally Posted by glt View Post
If you wish to bypass the sample rate convert, the input sample frequency must match the output. This means you need two clocks: one for the 44.1 family and one for the 48K family. With the clock you specified, you will not be able to bypass the asrc for 44.1K material.
i was under the impression that, given the fact that i can also set the mode of the ASRC, i can concurrently set bypass and set both input and output to slave in order to accept 44.1kHz without resampling.

Quote:
Originally Posted by abraxalito View Post
What input sample rates are you proposing to accept? The 1704 will go up to only 96k with the DF1704.
i'm happy with 96kHz, as i chose the PCM1704 for its true multibit characteristic.

Quote:
Originally Posted by abraxalito View Post
Why select the slow roll off in the DF1704? Its performance looks 2-3bits poorer in stop band rejection than the normal setting.
but doesn't the slow rolloff exhibit less passband ripple?

Quote:
Originally Posted by abraxalito View Post
Oh, and while I'm asking questions... given that you're concerned about RF ingression from the mains, why toroidals?
i figured, while i can use a mains filter to reduce RFI from the mains, i can't really (save from a brilliant case layout) reduce stray flux from E-I cores et al... toroids pass that much more rf?

thanks for the feedback!

~ brad.
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Old 24th February 2010, 01:43 PM   #6
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Quote:
Originally Posted by geekysuavo View Post
i'm happy with 96kHz, as i chose the PCM1704 for its true multibit characteristic.
DACs generally perform worse when made to run faster. There's more error from settling time as a proportion of the total, also since there are more samples to output, there are more glitches. So I'd suggest getting rid of the DF1704 entirely and using just the SRC to get to a decent sample rate - it will go just above 200kHz.


Quote:
but doesn't the slow rolloff exhibit less passband ripple?
How have you worked out that it might? TI seems very, very coy about the close-in passband performance of the slow mode. A plot is very conspicuous by its absence from the datasheet.

Quote:
i figured, while i can use a mains filter to reduce RFI from the mains, i can't really (save from a brilliant case layout) reduce stray flux from E-I cores et al... toroids pass that much more rf?
Toroids suffer from the disadvantage of having overlapping primary and secondary windings, giving them high inter-winding capacitance, hence much more RF. This can be mitigated somewhat with an electrostatic screen connected to earth. Your point about stray flux is a good one - you could use a bigger case and put the transformer further away as one solution. Screening against stray magnetic flux is rather difficult, even for seasoned professionals. Toroids do suffer from some stray flux too, given that their windings aren't completely axi-symmetrical, so it pays to be able to rotate them to get the lowest induced hum.
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Old 24th February 2010, 02:01 PM   #7
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Quote:
Originally Posted by abraxalito View Post
So I'd suggest getting rid of the DF1704 entirely and using just the SRC to get to a decent sample rate - it will go just above 200kHz.
i'm a bit puzzled by this. the DF is required to split the data from the SRC into left- and right-channel information... where is "just above 200kHz" coming from?

Quote:
Originally Posted by abraxalito View Post
How have you worked out that it might? TI seems very, very coy about the close-in passband performance of the slow mode. A plot is very conspicuous by its absence from the datasheet.
so i'm better off in all departments to use the fast rolloff in the DF? i guess i should do an in-depth read of the AD1896 datasheet.

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Originally Posted by abraxalito View Post
Toroids suffer from the disadvantage of having overlapping primary and secondary windings, giving them high inter-winding capacitance, hence much more RF. ...
thanks for that tip, i'll keep that in mind!

~ brad.
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Old 24th February 2010, 08:19 PM   #8
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so i'm better off in all departments to use the fast rolloff in the DF?
haha, ok i feel a bit stupid. i was somehow mentally connecting the slow rolloff mode of the DF with slow servo loop mode (long group delay) of the ASRC... hence my stupid comment about reading the AD1896 datasheet, which i did, only to (a) gain a better understanding of ASRC operation and (b) realize the chip in question was the DF.

ok, yeah, i can see that the fast rolloff of the DF would be better in terms of stopband rejection...

~ brad.
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Old 25th February 2010, 12:25 AM   #9
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Default Oversampling or not

Quote:
Originally Posted by geekysuavo View Post
i'm a bit puzzled by this. the DF is required to split the data from the SRC into left- and right-channel information... where is "just above 200kHz" coming from?
OK, so now my turn to feel a bit stupid Yeah, the DF is doing the splitting of the multiplexed audio bus into separate L/R channels, something I'd missed on the first pass. But also it upsamples by a factor of 8. Its this second aspect I was thinking you may well be better off without. Running with an input frequency of 96kHz, your DACs will be blazing away at 768kHz which is definitely going to degrade things.

But of course if we threw out the DF, we'd need to find another way to get the data in the right format to feed to the PCM1704s, so I guess I'd have to think about how to do that the best way... Hmmm.

The 200kHz figure I introduced is the max output frequency of the SRC (actually 212kHz), which means for 96kHz you'd only be getting an oversampling factor of 2.2. However oversampling was introduced as a means to simplify the output filter - the audio bandwidth remains the same, so in my view, if 4X oversampling was good enough for 44k1, then 2X is good enough for 96kHz. Have a look at Dan Lavry's website if you'd like to find out more.
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Old 25th February 2010, 04:25 AM   #10
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Quote:
Originally Posted by geekysuavo View Post
low(er)-voltage regulators:
the logic voltage regulators are salas shunts just like the i/v converter regulator, but they all output 12V. they're followed immediately by TL431 shunt regulators, which regulate that voltage down to the proper value, which will be adjustable by trimpots. all mosfet shunts are sinking at least 20mA under load. (as per simulations)
This confuses me; what is the reason for following the shunt reg with a tl431?
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