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DSP Board Completed (DSP56371)
Took me a while but I've just finished the first revision of my DSP board with SE and USB inputs. This is a pretty nice project and I was thrilled to find that Freescale has a good evaluation board called the SoundBite and has Eagle files of that board to download.
I don't think this board is perfect -- and I still have to figure out how to solder all those 0805 resistors without going mad -- but I'd like if a you could take a look and make sure I didn't miss anything. I'm making the eagle files available for you to play and give better feedback; please be aware that I make no guaranties this will work. If you like this you are free to buy me something from my Amazon wish list :) The DSP is set to boot of from SPI in slave mode as I will have another board for the UI (we're looking at a QVGA LCD with Atmel's qTouch like a QT60168). Download DSP with RCA and USB & RevA (zip) http://screenshot.ca/wp-content/uplo...AIN-Bottom.png http://screenshot.ca/wp-content/uplo...-RCAIN-Top.png Thank you for your comments :D I'm off to bed before I think of revision B... ahh too late - it's too large. 'll expose the ESAI with headers and put the ADC/DAC on another board that we will mount on top of the DSP board. |
Nice work! Yeah I think it's a good idea to separate the boards and make things modular. I did so with my DAC and i'm very glad I did because it enables me to try out new ideas without throwing all the old stuff away.
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I too think Its a good idea to use an ASRC like CS8422 to precede the digital signal processing, then, with fix clock/sample rate, you dont have to alter coefficients ever because of that. This DSP seems capable of some decent FIR stuff @ around 60khz. What you have in mind?
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I dont think you want to go there, these IC-s are far more sophisticated than what you can come up within a ~year?? ASRC is , lets see, DPLL, ratio estimation, curve fitting, much much more complited than your average oversampling filter ! Basically you also spare the first stage of oversampling because of the ASRC chip, that is , not bad to start with.
Dont forget also FIR filters are grossly inefficient at 96khz . |
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ok then why dont you say he can just redesign his PCB around some different clock generation scheme, that can take up a year in itself. I doubt ASRC matters anything once he has crossover in mind, if thats IIR, he sets 200khz output from asrc and spare a lot, or , if he wants FIR, he sets 60khz. Not everyone is dCS or Wadia to mess around for years with an oversampling filter in itself! :fight: |
lets see what Ed Meitner came up with :
MFAST™ vs. conventional PLLs Most converters utilize PLL (Phase Locked Loop) circuits. MFAST™ has two distinct advantages. It's a high-speed asynchronous system that locks almost instantaneously to any data stream. Moreover, unlike PLLs which merely attenuate jitter, MFAST™ strips jitter out of the audio stream completely. Enabling you to enjoy pristine sonic clarity whether the incoming data stream is pure or anything but. The DAC2 also features: :worship: |
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