Anybody using the new ESS Vout DAC (ES9022)? - Page 49 - diyAudio
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Old 16th October 2012, 06:03 PM   #481
CFT is offline CFT  United States
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Joachim's buffer could also be used for NOS dacs to "help clean up the HF dirt", could it?

Read with interest the comparison of PCM1704 and PCM1794 (filter disable) - with and without external filtering (FPGA filter or filtering in software) by John Swenson.
(Google: Tony's Player, John Swenson)

BTW, thanks very much to you guys that have involved on the design and the GB of the buffer : )
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Old 27th December 2012, 10:31 PM   #482
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Got my board today, but no BOM. Anyone have a digital copy?
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Old 27th December 2012, 11:16 PM   #483
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To which board do you refer?
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Old 3rd January 2013, 08:59 AM   #484
syklab is offline syklab  Hong Kong
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Hi WK,
Attach are the close-up on the buffer, the 0603 package is just a bit too small for my eye. Although only a few passive components but I couldn't find the fault on the right channel.

Left channel (working)
Voltage measure across
R7 and R8 is 0.143V
R1 is 0
R2 is 0

Right channel (not working)
Voltage measure across
R7 and R8 is 0.496 (-Vs) and 0.491 (+Vs)
R1 is 5.226
R2 is 2.36

Thanks for your help.

Click the image to open in full size.

Click the image to open in full size.

Click the image to open in full size.

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Old 3rd January 2013, 09:26 AM   #485
EUVL is offline EUVL  Europe
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The 100R resistor of the right channel next to the silk screened letters "Gnd" is shorted to the JFET cascode source pin (first photo top right).

Suck out the solder with a solder wick to see if it will work.
If not I am afraid you might need to have the FETs replaced.

We'll mask off those pads in Batch 2 to avoid such "accidents".
But it also helps when you check the boards thoroughly for such soldering errors before power up.

It is also a great help to use a ring lamp with a magnifying glass in the middle for AMD work.
Works fine even down to 0402s for my 50+ years old eyes, with short sightedness on top.


Patrick
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Old 3rd January 2013, 09:39 AM   #486
EUVL is offline EUVL  Europe
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Also judging from the photos, you seem to be using a ceramic cap instead of the Panasonic PPS film cap we recommended :
Joachim Gerhard Filter Buffer for ES9022

IMHO this will make a significant difference in results.
Suggest you try the Panasonic caps to convince yourself.


Patrick
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Old 3rd January 2013, 09:42 AM   #487
syklab is offline syklab  Hong Kong
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Hi Patrick,
Thanks for the quick observation, You got to have better eye than my. Will remove solder see if the jfet are still good or not.

Thanks
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Old 3rd January 2013, 10:58 AM   #488
syklab is offline syklab  Hong Kong
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Quote:
Originally Posted by EUVL View Post
Also judging from the photos, you seem to be using a ceramic cap instead of the Panasonic PPS film cap we recommended :
Joachim Gerhard Filter Buffer for ES9022

IMHO this will make a significant difference in results.
Suggest you try the Panasonic caps to convince yourself.


Patrick
Couldn't get the 0603 Panasonic PPS film cap from Element14 so I use the MLCC instead, will try PPS when I batch enough to meet Mouser's/Digikey minimum order.

Thanks
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Old 4th January 2013, 07:23 AM   #489
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@ EUVL (and all)

I am about to setup my own ES9023 system with WM8805 and JG Filter Buffer (could have joined the several GB but wanted to DIY ).

In post #58 you mentioned using two flip flops to devide the masterclock 1:4 for SD player (or WM8805?). What about the propagation delay of the flip flops? As per the datasheets the delay is about 2-10ns per flip-flop which sums up to a 4-20ns delay for the 1:4 devider. This is in the order of a period of the masterclock. Will the system still work in synchronous mode or will it work in asynchronous mode due to the delay (MCLK phase shift)?

Furthermore random phase jitter of good clock oszilators is specified as arround 1ps. For the propagation delay of the flip-flops the datasheet only specify min. and max. values (component variation?). Do you have any information about the variation of the propagation delay for a single flip-flop (that would add jitter)?

Best regards, Daniel
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Old 4th January 2013, 09:08 AM   #490
EUVL is offline EUVL  Europe
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Firstly for Red book CD, LRCK = 44.1kHz, BCK = 2.8224MHz, SCK =45.1584MHz in my case.
So there are 16 system clock pulses within one bit clock.

There is next to no information in the ES9023 datasheet regarding timing requirement between SD, BCK & LRCK to SCK.

However, on P.12 of the PCM5102 datasheet, “The PCM510x requires the synchronization of LRCK and system clock, but does not need a specific phase relation between LRCK and system clock.” I have no reason not to believe that it does not hold for ES9022 and the like.

On my original QA550 PCB, for example, the 11.28MHz XO feeds both the dsPIC and the SCK output directly. The dsPIC itself have multiple internal delays in double digit ns if I am not wrong. In comparison, the D-FF I use in my frequency divider has a propagation delay of under 1ns. Information from the manufacturer’s technical service indicates that the additional jitter per FF is < 1ps.

I don't claim to be a DAC expert by any means, but my understanding is that as long as SD, BCK and LRCK is synchronised relative to each other, and that they have the same base frequency of the SCK, which exact pulse of the SCK it is locked onto by the DAC does not matter. The synchronisation of SD, BCK and LRCK is implemented by your digital source (good or bad), and the fact that the same XO drives both the DAC and the digital source means that they are always in syn (phase relationship constant).

The SPDIF input of the WM8804(5) is of course a totally different matter. I am sure you know there is a PLL inside the WM8804, as it is necessary.

Hope this helps.


Patrick
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