SDIF-3 , SDIF-2 and DSD input of ESS Dac

[NeoY2k]

I think I got the answer:
http://www.ams-neve.com/Sites/8/File...ser_Manual.pdf

PDF page 7

DSD
Selecting DSD will default to 44.1kHz reference. If no sync is available it will use the internal crystal
reference.
The interface requires a minimum of two BNC cables (DSD L and DSD R) to the DSD DAC.
The DSD output is switchable between SDIF2 and SDIF3 with the rear panel dip switch. SDIF2
requires a 44.1kHz sync signal to be passed to the DAC and this should preferably come from the
1073DPD sync output via a third BNC cable. SDIF3 transmits the DSD signals with clock
information included and should not need the sync signal.
Refer to your DAC for compatibility information.

That shows that:
- SDIF-2 is a 3-wire transmission, with a 44.1kHz wordclock (while the ESS waits for a bit clock) => a PLL is needed
- SDIF-3 is biphase encoded, thus doesn't need an external sync line. A PLL will be needed to extract the clock from the datastream.

But that still needs to be comfirmed

[kevinkr]

Good work digging up that information..

[NeoY2k]

Thank you.
It should be on some IEC paper, but I can't find it...

Further inspection into the ESS datasheet showed that it will accomodate for both biphase and normal encoded DSD Data, but will anyway require a bit clock at the DSD Fs.


From the grimm's paper:
3.Overview
This interface is based upon 75ohm BNC, unbalance transmission, 1channel in one cable and
externalwordclock(WCK).Anditsbitrateis5.6448MbPS(f sdsd=2.8224Mbps)or
11.2896Mbps(fsdsd = 5.6448Mbps). Transmission is 1channel unbalance transmission and it
uses word clock as synchronization technique.

BUT

5-1 Modulation Method.
Phase Modulation
Bit rate= 5.6448Mbps when fsdsd is 2.8224MHz.
=11.2896Mbps when fsdsd is 5.6448MHz.

So this document fails to make the difference between sdif-3 and sdif-2. I tend more to trust Neve than to trust some full of mistakes paper.

5-2  Word Clock
    Duty 50%(±10%)    frequency=44.1kHz

Okay so we transmit a wordclock at 1/64 or 1/128 the bit frequency, so we'll need a 64* or 128* times PLL


APPENDIX
As SDIF-3 format DIO interface sends WORD CLOCK and DATA in different BNC cable, there
can be a difference in delay time between them. And also as SDIF-3 DATA is 88.5ns period
high-speed signal, there is a possibility of bit shift of data.  Consideration on selection of BNC
cable and connection is needed to avoid this data bit shift.

Again, this is SDIF-2, but with biphase encoded DATA, when it only applies to SDIF-3

This document drives me mad.

[fmak]

Originally Posted by NeoY2k

Hello,
I have trouble to find accurate description of SDIF-2 and SDIF-3 for DSD.
I mean, for the ESS chips are 3 inputs: Clock, Left and Right.

Nicolas

Just Google sdif 2 and sdif 3; the info is clear. As for ESS, all ypu needs to do is to feed in dsd(R) dsd(L) and clk.

If you want clarity, then try to find the manual for the dCS 954. I do nt have it right now, but it was freely available a couple of years back. Both sdif2 and 4 work if you have the right combination of equipment.

[NeoY2k]

Hi fmak,
Of course I googled it, but info wasn't clear at all, unfortunately. That's why I'm asking here.

I'll try to find the dCs manual.
Thanks!
Nicolas

[fmak]

Originally Posted by NeoY2k

Hi fmak,
Of course I googled it, but info wasn't clear at all, unfortunately. That's why I'm asking here.

I'll try to find the dCs manual.
Thanks!
Nicolas

I can find the dCS manual in 3 days or so, but the info in google.co.uk is good.

I have been using the interface for sometime on my dCS setup

[fmak]

Originally Posted by fmak

I can find the dCS manual in 3 days or so, but the info in google.co.uk is good.

I have been using the interface for sometime on my dCS setup

The thing that may have confused you is that sdif 2 refers to the two sockets for signals (L and R) and a third socket is for the clock. Alternatively sdif 3 refers to clock being embedded in the signals.

Just feed DSDL DSDR and DSDClk into the Sabre implemented by TW and there are no problems.

I have the pdf but can't break it into pages to send you (long)

[NeoY2k]

Well, It shouldn't work, as is it clearly stated in the papers that the ESS part wants a BIT clock, and the SDIF2 protocols sends a WORD clock at 44.1kHz. So there's need for a PLL.

But maybe it is good...? I don't know! ESS also has 2 seperate DSD modes, one for biphase encoded data, and the other for straight data. But they don't talk about clock recovery!

[NeoY2k]

Hi,
Not found any more ressources.
Would you send me the pdf, no matter how long it is? My mailbox should handle it.
Thanks,
Nicolas

[fmak]

Originally Posted by NeoY2k

Hi,
Not found any more ressources.
Would you send me the pdf, no matter how long it is? My mailbox should handle it.
Thanks,
Nicolas

What's your email; i have extracted the pages?