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Old 27th November 2009, 11:03 PM   #71
jkeny is offline jkeny  Ireland
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Joe,
I have the datasheet & can give some of the info that has already been revealed publicly by Dustin - each DAC puts out 0.924*AVCC = 3.04V PP on the analog outs - it also puts out 0.924*4.244mA = 3.903mA PP (so 4*3.903 = 15.6mA PP for 4 channels) with a bias of AVCC/2 (1.65V)
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Old 27th November 2009, 11:29 PM   #72
acko is offline acko  Australia
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Hi Everyone,

Sorry for the delays but the design team has been working very hard to provide a highly optimised layout and options to bring out the best from the Sabre chips.

Prototype boards are due out next week for tests and will post updates soon.

As for queries on Schematic/design info of Sabre chips on public domain, we need to abide by NDA restrictions (sorry). But negotiating to allow those who purchase the DAC unit itself to have schematic included in the user's manual for reference purposes. Will see how this goes.

Thank you for your patience.


Regards, Acko

Last edited by acko; 27th November 2009 at 11:31 PM.
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Old 27th November 2009, 11:33 PM   #73
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Quote:
Originally Posted by jkeny View Post
Joe,
I have the datasheet & can give some of the info that has already been revealed publicly by Dustin - each DAC puts out 0.924*AVCC = 3.04V PP on the analog outs - it also puts out 0.924*4.244mA = 3.903mA PP (so 4*3.903 = 15.6mA PP for 4 channels) with a bias of AVCC/2 (1.65V)
Thanks.

The voltage outs have "+" and "-" outputs, in which case 3.04V PP is would be across those and the outputs sits on 1.65V. That makes sense. Is this an internal opamp solution? If it's an inbuilt I/V then the current output would be disabled if used in voltage mode. If both are available at the same time, then an I/V is not used for voltage outs. The volts would have to be derived separately.

Now for the current outputs, the current output is certainly healthy, no doubt because of paralelled DACs. But if what you call bias is what I call offset voltage then the I/V conversion has to float on 1.65V whereas B-B PCM/DSD/1792/1794 etc does not, no DC on the output. The I/V converter I use thrive on the B-B's 0V (and other which are the same) but are a pain when I have used it with AD1955 (2.39V). Does the ESS have a Vref 1.65V or does that have to be generated externally.

Also, does it have a bias/offset current. In the case of AD1955 it's 3.04mA - if zero that's makes it simpler than AD1955.

You know, stuff like this should be available, absolutely no reason whatsoever that it shouldn't.

But thanks anyway. Anything you have along these lines are appreciated.

Cheers.

Joe
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Old 16th December 2009, 08:16 PM   #74
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Hi acko,
Do you plan to use asynchronous sample rate converter and Class a discrete output in this project
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Old 29th December 2009, 06:09 AM   #75
acko is offline acko  Australia
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Default ackoDAC Preview

Hi Everyone,

I am nearing completion of the new DAC version and also all the support modules required to build up a complete system. See attached files for preview. All these will go for fab next week and boards should be ready by mid-Jan for assembly/test and then release. Happy New Year!
Acko
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File Type: zip ackoDAC Preview.zip (918.3 KB, 663 views)
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Old 29th December 2009, 07:28 AM   #76
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Quote:
Originally Posted by acko View Post
Hi Everyone,

I am nearing completion of the new DAC version and also all the support modules required to build up a complete system. See attached files for preview. All these will go for fab next week and boards should be ready by mid-Jan...
I am quite interested in what you are doing, despite my being miffed at ESS unfriendly policies, and have some questions:

A. What do you use as I/V converter? Surely no NDA can prevent you from revealing that. This is such a key to great performance even with the best of DACs.

B. What or where is the source of clocking. What if I use the SPDIF, does the transport become the "master" and the DAC "slave." I don't necessarily pooh-pooh that out of hand as some would. But if this is the case, the transport (if used with such) becomes crucial. Or can the clocking easily be incorporated/updated. Very much feel this is a BIG part of getting the best that digital audio can do.

Link to Terra Firma Article.

C. If able to come around to my place I would like to discuss with you a simple and yet confidential trick that you may not be aware off, one that I am sure can be applied to your PCB (close to where the DAC is located... hint) without any changes. Would also love to hear it at the same time.

Cheers.

Joe R.
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Last edited by Joe Rasmussen; 29th December 2009 at 07:33 AM.
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Old 29th December 2009, 07:45 AM   #77
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Oh, just did notice X1 near ESS chip. Looks like a 3.3V SMD powered oscillator? What frequency, allowed to tell? And what type or source? Is it powered off a 3.3V rail shared by the ESS DAC or a separate regulator/supply? This last one has huge influence on the sound, even more than choice of low jitter oscillator.

Cheers.

Joe R.
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Old 29th December 2009, 03:30 PM   #78
jkeny is offline jkeny  Ireland
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Hey Joe R, I see you back again - I gave you some ESS info privately & asked about your IV stage but got nada in reply - is your mail system broken or what?

PS. if you look at the files contained in ACko's zip your answers are already there.
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Old 1st January 2010, 11:53 AM   #79
qusp is offline qusp  Australia
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yes joe, you might consider reading the info all your questions and more are answered. the I/V stage is what you make it. there is an opamp version available or you can use whatever you wish, beit tubes transformers buffers etc etc. same with regulation. all regulation points are exposed and very near their target.
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Old 2nd January 2010, 01:13 AM   #80
Pano is offline Pano  United States
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I've PM'd Joe too about ESS info and heard nothing. Maybe he's not seeing his PMs or emails?
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