|Digital Line Level DACs, Digital Crossovers, Equalizers, etc.|
Please consider donating to help us continue to serve you.
Ads on/off / Custom Title / More PMs / More album space / Advanced printing & mass image saving
||Thread Tools||Search this Thread|
|15th July 2009, 04:03 PM||#1|
Join Date: Dec 2007
One more SPDIF thread
I know this subject has been beaten to death.
But I'd like anyway to ask a few questions and post suggestions, because I may (and sure am) be wrong on many aspects, and would like to know your opinion on it.
Let's describe the project: a switchable multi input circuit, that should handle AES/EBU, SPDIF, Toslink, i2s over BNC, ADAT, i2s LVDS over HDMI cable and DSD.
Formats will remain in their native form but translated to CMOS level (logical level, so there will be a comparator somewhere).
It will be followed by an ES9018 DAC. This is important because
A] It will handle SPDIF, i2s and DSD decoding on its own so I don't need any CS spdif receiver or stuff like that.
B] It's meant to be a jitter killer. As far as I understood it (I don't clearly understand the white paper) it will:
- Sample the SPDIF CMOS input with a 80Mhz clock
- Correct duty cycle to 50%
- Extract and store the bit value
- Timestamp the word edge (40Mhz clock)
- Estimate from last samples what is the average sampling frequency
-At the next word clock edge, interpolate/extrapolate in it's own 48 bits DSP what is the corresponding value at this time, from the curve that would have been drawn if this clock edge arrived when it "should", computed from the average samplig rate.
- Send it to it's DAC section, insane filtering, etc...
- And many other thins I don't know, but I think it gives an idea.
C] It measures up to 135dB DNR (in mono mode). 350ps jitter is 1 LSB error on 16 bits, and this DAC has way more DNR than 16 bits, so I think jitter reduction IS very efficient. Plus eval boards have nothing special about their SPDIF input...
OK so I need to feed a comparated input to this DAC.
This is the path signal will follow:
Transmission line =>Connector=>Termination and input circuit=>Buffer=>Switcher=>Comparator=>DAC.
1st guess is: I only want one comparator. More would just ADD jitter.
2nd thought is: AD8130 buffer (well, it's not a buffer, both input are high Z... read the datasheet for more info, it's a video 220Mhz opamp) has an Enable input, thus making source switching easy. That's part why I choosed to work with it.
I'd like to discuss these problems in the signal flow, so:
1st: The connector to choose, adapters, compensation
2nd: Different input schemes, with or without transformer, with or without caps, their limitations, potential problems, are they valid, can they be simply improved, do we need bandwith limiting, has the EN function enough isolation to prevent crosstalk etc...
3rd: Comparator. With any of the input stages I have in mind, disconnecting the cable leads to 0V output. So you need hysteresis (how much) or shifting the comparison level (which is worse? which is safer? Without hysteresis, won't HF noise give false transition edges? etc).
This is a huge subject, so let's start with the first point. We'll move on to the next only when we'll have a clear idea of problems and potential solutions.
Next post will ask about input connector and transmission line!
|15th July 2009, 04:09 PM||#2|
Join Date: Jun 2004
IMHO both bandwidth limiting and hysteresis increase data-related jitter and should be avoided. Why worry about false triggering without anything connected?
|15th July 2009, 04:17 PM||#3|
Join Date: Aug 2008
i think its plain 256x (or even more? ) oversampling followed by linear interpolation ~> asrc... They get away with linear interpolation instead of polynomial because of "insane" amount of OS.
|15th July 2009, 04:41 PM||#4|
Join Date: Dec 2007
Ok so start with the cable and connector problem.
I will concentrate on SPDIF, problems will remain for other formats, but I'd ask these questions way later.
What we would like to see would be a 75 ohms coax, with 75 ohms BNC on each end. Proper 75Ohms termination is not yet the question.
First: Even if we had that, we have:
- Cable impedance tolerance (+/- 3 Ohms)
- Cable impedance asymetry
- Cable ends impedance jump (you had to open the cable to put the connector)
- Cable end connector impedance
- Socket connector impedance
Cable impedance tolerance, and cable impedance asymetry can't be taken care on a general basis. It may be solved by analyzing each cable with a TDR. But this is out of control in most situations (and it is in mine). Jocko pointed out he obtained better results with higher attenuation cables as these will absorb more of the reflections, and while it probably is true, I want to consider it as out of control (it will be used on field, will move, etc...)
Cable end impedance and connector induced impedance may be estimated, and maybe corrected. But this would be usefull at best with a particuliar cable model and plug model. I prefer to consider this enough out of control. But maybe could we find a constant, and maybe correct it?
The BNC socket should be a perfect 75 Ohms. Jocko showed it was not the case, and if I remember correctly, he found a way to compensate for it with an additional cap. This will only work for one model of BNC socket, but as I buy and solder them, I'm in control of this (more or less, production tolerances apply, and I want cheap connectors, I will NOT spend 20$ for a socket).
How much is this? Should we care? I can't guess any info from datasheets, could it only be found by TDR analysis?
Then we have more of real world. Few devices have a 75R BNC output. Most people don't have these cables in stock.
In other words: I want to be able to connect RCA plugs.
Say I don't use a BNC socket, but a RCA one. These are all but 75R, more or the 30-40R. Given propre 75R cable was used (and considering only the receiving end), it will at worst travel 2cm of 30R transmission line. While it is not good for sure, it is low enough not to kill the signal. But it will for sure have some reflections, thus adding distortion to the signal, thus moving the edges.
Now it isn't 75R, but as it is soldered on board, it could be measured, and corrected for. If we can extract a constant from RCA plugs, we could add it too, and make for something with a RCA plug that would look more like a 75R transmission line.
This is only fine if I solder an RCA socket, I loose the BNC/RCA adaptor option on this input. Would it be better to have seperate BNC and RCA inputs, so each could be corrected?
Or should I forget about this correction for RCA sockets, only make BNC inputs, and use BNC/RCA adapters?
How good/bad these adaptors are?
As they are an option on the line, I can't have any correction. But at least they are really coaxial, so they may not be that bad. I don't know.
Regarding the XLR input for AES/EBU, same problem as with RCA, except that I don't have to worry about an adapter. XLR plug and XLR socket are not 110 Ohms. They may be corrected. Plug impedance trouble could be taken in for this correction, especially as nearly everyone uses Neutrik, at least in pro domain.
What do you think about that? Any suggestion? Do you know how to compute corrections for these connectors? Can it only be measured from real world connector using a TDR/VNA?
The only TDR/VNA I could afford would be the mini VNA. It has low dynamic range (50cB), not adjustable output (0dbm), 100kHz-180Mhz, and probably 50R input BNC. Would it be any use? I wouldn't buy it right now anyway, so if it only can be measured, let's find some value and imagine. Measuring it later will give the answer.
|16th July 2009, 11:37 AM||#5|
Join Date: Dec 2007
Tritosine: Thank you. The white paper is somehow hard to understand.
Well, I think (but I may be wrong) that Low freq bandwith limiting is good.
LF Noise and DC components are not wanted. A DC differential component will move the decision point and then affect the duty cycle.
Well, let's not strictly follow the signal flow (I think this impedance stuff annoys almost everyone). Let's think about the out of the buffering stage and the comparator stage.
About false triggering etc, that's what I have in mind:
Referencing to ground, adding say 10x gain, and comparing to 2.5V reference means that you think that the signal is 0.5V pp and that it has no DC differential component.
While you got rid of DC and LF with a transformer (if you use one), you still assume a 0.5Vpp signal. What if your signal really is 0.45V pp? You shifted the reference above the original crossing point, and you modified the duty cycle of the recovered signal.
Now, if you remove the DC component (and do not further add one by grounding one end of the secondary of the trafo, if you use one), your signal will be centered around zero. Your switching point is no more correlated to the pp value.
Given that you could compare exactly at the zero and that no HF noise would cause false triggering.
The price to pay is that if you unconnect the source, you have 0V to compare with 0V. I would not bet it won't oscillate, while you wouldn't have had this problem if your comparison point was arbitrary.
Now or you use an arbitrary decision point:
G=10 and 2.5V ref point (usually done) and your duty cycle asymetry is due to the incoming signal. If it's perfect 0.5V pp you're fine. The further it is from 0.5Vpp the worst it is. And impedance mismatch WILL modify amplitude. I wouldn't rely on this...
Or you make your signal float around DC (for comparing at 0) and shift decision point above noise floor, say 70mV. Now you have a modified duty cycle, it is no more due to the input signal but to your input circuitry.
Now what about hysteresis?
I know Jocko hates it, but:
If your signal has the same ramp up and ramp down slopes (it won't be exactly the same, of course).
IF your hysteresis is symmetrical around the ref (VERY IMPORTANT).
Imagine a bandwith limited square wave perfectly centered around ref. If the hysteresis is symmetrical, all that it will introduce is a constant delay! And that's something we don't care.
Now, what will move the decision point is distortion of the signal. The greater the hysteresis, the more sensitive to distortion it will be, but the lower to noise. We don't fear unconnected input anymore as long as it's higher than noise floor for 75R load.
We are no more related to DC offset, PP amplitude, we still are to signal distortion.
Rho (impedance mismatch) of the input, and it's variation with frequency, will unfortunately bring distortion.
Then the HF limiting question comes into play. If we hadn't hysteresis, we would really have to fear HF noise.
HF makes for sharper edges if it is in phase. But if it isn't, it makes for distortion. And we don't want it.
If you think about it, you have the original modulation, were the HF harmonics really phase controlled? Was their phase altered along the transmission?
After all, as we now compare at the half of the amplitude of the original signal, if we bandwith limit it down to say a PERFECT sine, the decision point has not moved. Zero times anything is zero...
The problem is you can dream about this perfect sine, you just won't have it. Distortion moves the decision point, so the slower the slope, the more chances it has to have distortion that will induce more change in timing.
There's no free lunch and I quite bite the dust there. There must be a compromise. My buffers have a 220Mhz bandwith so it is already somewhat limited. If you use a transformer, your HF has been eaten a long time ago already! Maybe would it be a good idea to limit HF content to say the 5Th harmonic, and that is 150Mhz for 192kHz (well, a bit less actually).
Another problem of relying on signal distortion is that I really fear to use a trafo or anything not "pure" resistive over wideband on input. Its impedance is not constant over the full transmitted frequency range, so it will introduce distortion by reflections. You would have to make it linear from nearly DC to say 250Mhz. Eeeeeee...
So the next question to answer will be: what input stage.
But that probably is enough for now!!!!!!
Any comments, suggestions, explanations, on the above? Or on my connector impedance stuff of the previous post... Or anything....
I hope I don't sound like someone knowing what he does. This is not "hey this is the way to do it", these are just ideas I had and they may be COMPLETELY WRONG.
I'm not Jocko nor Guido. In fact, I nearly missed my EE degree because I was really bad at RF... And, even if I understand transmission lines, I don't even remember how to use a smith chart...
|16th July 2009, 04:55 PM||#6|
Join Date: Nov 2004
Location: Central Ohio
just a few comments to throw in.
It is USD $2.17
A nut and lock washer also must be bought under different part numbers.
I bought some for a prototype and they seem to work well, but I don't have a TDR. Digikey has them too.
If you get the chance to test them with a TDR, I would like to know the results. I don't see what $20 will get you other than gold plating.
An impedance discontinuity very close to the driver will not matter as much as a discontinuity elsewhere in the transmission line. Hopefully the driver impedance will swamp out the effect of a RCA very close to the driver.
Also, you may be able to correct the driver end with a RC termination that accounts for the RCA impedance.
A discontinuity in the middle of the transmission line would be very bad.
When the cable is removed and if the comparator oscillates it doesn't really matter, does it? Somebody already mentioned that.
It may take a few milliseconds to lock when you put the cable back on.
So, something can cause a glitch in the area where the eye pattern crossover decision is made.
Jocko is against it because the hysteresis circuit uses feedback and the feedback energy is fed back into the transmission line. It's a trade-off that you must evaluate and make a decision. Maybe a very small amount of hysteresis?
If the hysteresis causes a non-50% duty cycle, the ESS chip will correct for it. theoretically. It seems to do a good job on SPDIF. Other DAC chips are much more sensitive to SPDIF problems.
A TDR may give incorrect results since your coupling caps and transformers have higher impedance at above 250Mhz frequencies. a 50pS risetime edge from a TDR will be distorted by the transformer.
|17th July 2009, 12:50 PM||#7|
Join Date: Jun 2004
I thought you meant HF limiting, I agree on LF limiting.
About hysteresis, it's already been answered above: a hysteretic input is also a generator of signals not present in the original signal.
|28th July 2009, 02:45 PM||#8|
Join Date: Dec 2007
Hello, I'm back!
Well, I understand that hysteretic inputs spit signal back into the transmission line. But there will be a buffer between the input and this comparator anyway, and the AD8130 is in reality 3 opamps in one (see datasheet) so I don't think any significant amount of energy could be coupled back to the input!
Maybe using one more AD8130 just a few mm before the comparator would avoid any distortion generated between the input buffer and the comparator.
Regarding oscillations for unconnected input, well, oscillating will make fast components heat, overheat, and die. Maybe not the first time, nor the second, but from the lifetime point of view I can't agree about letting a component oscillate...
Right now, my problem is about frequency limiting. As I said, sharper edges make for sharper transition, if the high frequencies are in phase. And chances are that at high frequencies, they are not. Not at all in most cases. They will just create HF garbage, thus HF jitter. If I bandwith limit, I shift the problem, no more HF jitter but more lower frequency jitter. But probably a lot less, don't you think? Any more ideas about it?
P.S: Ok, forget about following a logical progression, I want to switch signals.
I can do it with an analog switch/multiplexer. Then I only have one buffer: It saved me components.
Or I can use one buffer for each input, and use their Enable function.
Analog mux makes for less components, but more complex routing, and longer lines on the "transmission line" input, prior the buffer. Plus analog mux is expensive, and I nearly could buy all the buffers needed for the same price than the mux chips.
On the other hand, these buffers present a 10pF to ground when in shutdown mode. Given the very low output impedance (I don't remember, something under 0.1R) and the very high impunt impedance of the next stage (probably between 5 and 10 MR) I don't think we care.
So, any reason to choose mux and not disable buffers?
|Thread Tools||Search this Thread|
|Thread||Thread Starter||Forum||Replies||Last Post|
|SPDIF on cdrom to SPDIF on Digi Crossover||davidallancole||Digital Source||0||11th January 2007 04:26 AM|
|cdrom spdif quality / sound card spdif||metebalci||Digital Source||0||2nd September 2006 08:16 PM|
|spdif out to double spdif in||balthazard||Digital Source||0||1st March 2005 07:52 AM|
|SPDIF: VCC / SPDIF which way round?||rogercameron||Digital Source||6||18th April 2004 11:29 AM|
|New To Site?||Need Help?|