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Old 30th July 2009, 05:54 PM   #61
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Quote:
Originally posted by Thor66

According to Borbely, the SRC4392 can interpolate without introducing ringing. But SRCs are accused of converting jitter into data and thus often having a signature of their own. Can anyone confirm this ?

How about using an SRC solely for interpolation and feeding it from a low jitter source ?
Looks like they have builtin zero order hold function in cpld before the ASRC to emulate the NOS thing, so it becomes a NOS alike / interpolation hybrid , with the same NOS artifacts as ever , and because of the SRC4392's own filter is set to work at very high frequencies ( up to 192 khz) its not really hurting the squarewave anymore, while they also gain the jitter discarding properties of the SRC . Interesting stuff...
You can check 96-> 44.1 ringing artifacts here:
http://src.infinitewave.ca/ , you see a few started to avoid preringing at the cost of "insane " phase shift.
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Old 30th July 2009, 06:05 PM   #62
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Quote:
How about using an SRC solely for interpolation and feeding it from a low jitter source ?
the no ringing property of the aforementioned circuit comes from the digital domain zero order hold function, eg. double, quadruple insertion of same successive samples. In a quadruple case its like incoming 44.1 - ZOH -> 176.4 -> ASRC -> ~210 khz and jitter discarded entirely. It must be better than your average NOS
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Old 30th July 2009, 06:07 PM   #63
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I have an idea.

4 DAC chips Iout parallel.

Data is updated always on one chip only, sample 1 chip 1, sample 2 chip 2, sample 4 chip 4, sample 5 chip 1 and so on.

The new data for the new sample is always the difference between the new data of the new sample and the sum of the current data of each chip.

Example: current data = 34A, combined by

chip 1 = 5A chip 2 = 9A chip 3 = 23A chip 4 = -3A

Next data = 41A
Next updated chip = chip 2
Next data for chip 2 = 16A


That would increase resolution, reduce glitch energy, and also mostly avoid the MSB transition at bipolar zero.

Full scale currents would need to be matched closely.
A digital servo implemented to avoid drifting of the data too much away from BPZ.
A prozessor to calculate the data values.
And perhaps to make a decision which chip needs to be updated so that all codes stay as close to BPZ or a small value above or below BPZ.
In the example that would be chip 4 with a new value of 4A.

16 x 20bit PCM1704 parallel would reach 24 bit resolution.
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Old 30th July 2009, 07:34 PM   #64
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http://www.essex.ac.uk/csee/research...lew%20rate.pdf

prof. Hawksford & co are some steps ahead in this "time interleaved" variant.
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Old 30th July 2009, 07:47 PM   #65
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Quote:
Originally posted by tritosine
http://www.essex.ac.uk/csee/research...lew%20rate.pdf

prof. Hawksford & co are some steps ahead in this "time interleaved" variant.

Are you sure ? This is again interpolation. My idea is non-interpolation.
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Old 31st July 2009, 08:25 AM   #66
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Hello Berhard,

Quote:
Originally posted by Bernhard
I have an idea ...(to) reduce glitch energy, and also mostly avoid the MSB transition at bipolar zero...
You can add dither to obtain same result.

Analog post filtering
About implementation of your analog filter, do you have schematic?

Thanks

Eric
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Old 31st July 2009, 02:38 PM   #67
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Bernhard, your solution looks like some sort of DEM... but...
pcm1704 , 18bit real world bits for 35 Eur, is not exactly my idea of spending money ...

on another note heres a great article:

http://www.meridian-audio.com/ara/coding2.pdf

look, they arrive at a format thats 14bit 58khz, give it a tought maybe : ))
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