I have a toslink output device (Airport Express), but my DAC is SPDIF only (RAKK DAC II). I purchased one of those cheap converters online, which functions, but I noticed I tend to get a number of 'hiccups' in the data stream, which are very audible as a brief silence in the audio.
Poked around a little bit, and saw that when I had the wall-wart plugged in (DC power for the converter), I would get detectable noise on the SPDIF ground. As a troubleshooting tool, I used a 9V battery in place of the wall-wart, and all problems were solved. No noise, no hiccups. I opened up the converter and was appalled at the construction quality. Replaced some capacitors with tantalum and cleaned up the solder joints, but to no avail. Definitely seems to be power related.
Doesn't surprise me, as the wall-wart is not the highest quality supply, and is likely not a shielded transformer or even split bobbin. So I proceeded to design my own converter, and have attached it for review.
Comments?
Poked around a little bit, and saw that when I had the wall-wart plugged in (DC power for the converter), I would get detectable noise on the SPDIF ground. As a troubleshooting tool, I used a 9V battery in place of the wall-wart, and all problems were solved. No noise, no hiccups. I opened up the converter and was appalled at the construction quality. Replaced some capacitors with tantalum and cleaned up the solder joints, but to no avail. Definitely seems to be power related.
Doesn't surprise me, as the wall-wart is not the highest quality supply, and is likely not a shielded transformer or even split bobbin. So I proceeded to design my own converter, and have attached it for review.
Comments?
Sure, that's not a bad idea, though I only have one optical device at present.
I guess my thought was trying to improve on the hex inverter implementation, using an amp more specifically designed for driving video type loads. It does put out a full 2.5V p-p at the receiver, which some might wince over. Knowing my D/A can accept this voltage, I actually think it to be an improvement over the 1V p-p specification.
If I haven't made any gross errors in the design, I'll move ahead with the build. Just hoping to get a sanity check before ordering circuit boards.
I guess my thought was trying to improve on the hex inverter implementation, using an amp more specifically designed for driving video type loads. It does put out a full 2.5V p-p at the receiver, which some might wince over. Knowing my D/A can accept this voltage, I actually think it to be an improvement over the 1V p-p specification.
If I haven't made any gross errors in the design, I'll move ahead with the build. Just hoping to get a sanity check before ordering circuit boards.
zigzagflux said:
Just a comment, you are sending, in essence, squared up data pulses through an analog op-amp with lots of feedback. This is sort of a mismatch in my mind. When I did this sort of thing in the past, I used a flip flop reclocker (i.e. HC74), driven by the onboard crystal oscillator. You could use the normal and inverted outputs to drive the output transformer, with divider resistors in front of it to give you the right level and impedance. This will optomize jitter performace.
Bob
Thanks for your reply. Allow me to play devil's advocate, so I can convince myself which method is preferred.
5V CMOS of the 74HC variety specifies a rise/fall time of about 500nsec at 4.5V. This equates to a slew rate of around 10V/usec, and assumes essentially no load (just 50pF capacitance). There is also some propogation delay on the order of 25nsec.
The AD8055, shows a slew rate around 1400V/usec, over 100 times as fast. And this is with a load of 100 ohms !! I would think the video amp would provide a much faster, sharper transition given the severe loading requirements. It would actually seem that the video amp would respond and settle in less time than the propogation delay of the digital logic alone. I could pursue faster logic families, but for the most part they are not designed to drive loads on the order of 150 ohms, further extending rise/fall times.
My rationale in taking this approach was that digital logic does not have the capability to drive the line adequately, nor is it as fast as one might think. Perhaps I am headed towards disaster, don't know.
5V CMOS of the 74HC variety specifies a rise/fall time of about 500nsec at 4.5V. This equates to a slew rate of around 10V/usec, and assumes essentially no load (just 50pF capacitance). There is also some propogation delay on the order of 25nsec.
The AD8055, shows a slew rate around 1400V/usec, over 100 times as fast. And this is with a load of 100 ohms !! I would think the video amp would provide a much faster, sharper transition given the severe loading requirements. It would actually seem that the video amp would respond and settle in less time than the propogation delay of the digital logic alone. I could pursue faster logic families, but for the most part they are not designed to drive loads on the order of 150 ohms, further extending rise/fall times.
My rationale in taking this approach was that digital logic does not have the capability to drive the line adequately, nor is it as fast as one might think. Perhaps I am headed towards disaster, don't know.
zigzagflux said:
On the transition times you quoted - 500ns - that is the maximum time for the *input*signals to the chip, and not the output transition times. I just looked at a 74HC74 data sheet, it says it can drive a fan out of 10 LSTTL loads - this is a lot of drive. Digital logic is made precisely for this sort of job.
http://www.onsemi.com/pub_link/Collateral/74HC74.PDF
The spec for the output transition time at 6V under normal temps is 13 ns. I've measured these, driving a single load I have measured 2ns rise and fall times on HC logic. I avoid the faster AC as it usually rings on the pulse edge transitions. I've actually built units like I describe, so it's not a theory thing. This was over 10 years ago, and they are all still working fine. Even better, I measured the jitter performance on the receive side, and the performance was much improved with the SPDIF re-clocking before output scheme.
Although it is most popular to reclock at the A/D input, it can also be used used to clean up timing on SPDIF signals. This may be another easy thing that is not widely used, as no one ever published it. I was going to, after the TAA RIP II Jitter article on re-clocking in '96, but never got around to it.
Yeah, I got the datasheet mixed up there.
Still, 13ns (or even your 2ns measurement with light load) is slower than the performance of the video amp. At 100 ohm loads, they show large signal step responses between 2 and 4ns. I would be shocked if the 74HC family could drive that fast at 150 ohms. Ten LSTTL loads seem pretty small in comparision to a 150 ohm load along with a coax cable and its capacitance. The AD8055 is rated for driving up to 4 video loads.
I'm not saying digital logic wouldn't work; after all, it's what I currently use. I just think the typical circuits can be improved. Whether or not it is audible is of course another story. I suspect the greatest gains for me will be in the improved power supply.
Still, 13ns (or even your 2ns measurement with light load) is slower than the performance of the video amp. At 100 ohm loads, they show large signal step responses between 2 and 4ns. I would be shocked if the 74HC family could drive that fast at 150 ohms. Ten LSTTL loads seem pretty small in comparision to a 150 ohm load along with a coax cable and its capacitance. The AD8055 is rated for driving up to 4 video loads.
I'm not saying digital logic wouldn't work; after all, it's what I currently use. I just think the typical circuits can be improved. Whether or not it is audible is of course another story. I suspect the greatest gains for me will be in the improved power supply.
Just an idea... LTC485
http://www.linear.com/pc/productDetail.jsp?navId=H0,C1,C1007,C1017,P2064
I think about using this one for Toslink-AES/EBU and/or SPDIF.
Br
Josch
http://www.linear.com/pc/productDetail.jsp?navId=H0,C1,C1007,C1017,P2064
I think about using this one for Toslink-AES/EBU and/or SPDIF.
Br
Josch
Hello Guido:
Nice to have you join in. Now that you mention it, it does make sense to place the resistor after the transformer. I will move it.
Since the receiving end has a Lundahl transformer, I would think the problem is from a poor power supply. Battery power for the converter works great. I do know the receiving end has the resistor on the D/A side of the transformer, not the cable side. Could you elaborate on the net effect this has?
Nice to have you join in. Now that you mention it, it does make sense to place the resistor after the transformer. I will move it.
Since the receiving end has a Lundahl transformer, I would think the problem is from a poor power supply. Battery power for the converter works great. I do know the receiving end has the resistor on the D/A side of the transformer, not the cable side. Could you elaborate on the net effect this has?
zigzagflux said:
Hi
It depends how the Luhndahl is connected. ie how the cabling is connected in terms of common mode. Anyhow, when battery-powering the circuit, you could stll induce a common mode effect by connecting the ground of the original wall supply to the ground of the circuit.
succes
zigzagflux said:
Well, if you have convinced yourself, go ahead and build it, then see how it does.
I'm telling you what I did over 10 years ago. If I was to do it today, I would likely do it different. You know, you need to treat it as the whole system, transmit and receive. Just talking about one side of it, without matching it to the other end, is not the best way to optimize it. But frankly, it sorta typical for the way people tend to think.
If you want to use a high feedback single ended analog op-amp to send digital signals, go for it. But don't condemn digital logic when driven by a $1.99 wall wart transformer, and then thing the digital logic is the problem
Bob
Got the circuit built, and have some fun graphs to display. First, the existing circuit, built with 5V HC logic:
Two basic observations I had: The output was a little lower than I would have liked, at +/-0.35V, instead of the specified 0.5V. I suspect, since it was functional, the CS8416 was able to read it just fine anyway. Rise times were around 5-6ns, with some ringing on the output (not transformer coupled).
Then, compare to the new design using AD8055 and output transformer:
Ringing now moved from the rising edge to the falling edge, but drive magnitude was higher at +/- 0.75V. Rise times were slower, too, at maybe 13ns. This bothered me, since it made little sense to me why the slew rate would be so poor. So, I took a look at the output of the torx converter, and saw this (purple is torx output, yellow transformer secondary):
So it looks like the AD8055 is doing exactly what it's being told to, and the slow transitions are due to the optical converter. Going back to the datasheet, this is reasonable performance from the optical converter. When motivated to build another circuit, I'll pursue a schmitt input gate just before the AD8055 (I think most SPDIF converters use schmitt gates). With the CMOS gate driving a high impedance, I hope to achieve below 2 ns transition with maybe an AHCT device. Now I'm not too sure how successful this will be, since decreasing transition times alone do not guarantee jitter improvement, but it could help. It does appear that the AD8055 and transformer have the bandwidth to permit the quicker transitions, though.
Next day or two I'll pull out the analog scope and look at the RF noise compared to the existing converter. And, of course, I need to listen to the device. Might be good enough as it currently stands; as long as I get rid of the hiccups, I'll be more than happy.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
Two basic observations I had: The output was a little lower than I would have liked, at +/-0.35V, instead of the specified 0.5V. I suspect, since it was functional, the CS8416 was able to read it just fine anyway. Rise times were around 5-6ns, with some ringing on the output (not transformer coupled).
Then, compare to the new design using AD8055 and output transformer:
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
Ringing now moved from the rising edge to the falling edge, but drive magnitude was higher at +/- 0.75V. Rise times were slower, too, at maybe 13ns. This bothered me, since it made little sense to me why the slew rate would be so poor. So, I took a look at the output of the torx converter, and saw this (purple is torx output, yellow transformer secondary):
An externally hosted image should be here but it was not working when we last tested it.
So it looks like the AD8055 is doing exactly what it's being told to, and the slow transitions are due to the optical converter. Going back to the datasheet, this is reasonable performance from the optical converter. When motivated to build another circuit, I'll pursue a schmitt input gate just before the AD8055 (I think most SPDIF converters use schmitt gates). With the CMOS gate driving a high impedance, I hope to achieve below 2 ns transition with maybe an AHCT device. Now I'm not too sure how successful this will be, since decreasing transition times alone do not guarantee jitter improvement, but it could help. It does appear that the AD8055 and transformer have the bandwidth to permit the quicker transitions, though.
Next day or two I'll pull out the analog scope and look at the RF noise compared to the existing converter. And, of course, I need to listen to the device. Might be good enough as it currently stands; as long as I get rid of the hiccups, I'll be more than happy.
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