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|18th February 2009, 03:53 PM||#1|
Please help with DIT4096 mode configuration
I'm making a SPDIF output from my car head unit. I've got mastercklock 16 mHz on it and the following outputs: SRDATA bit clock output, Left/right channel discrimination signal output and Serial data output which are connected to the proper DIT4096 pins. But I have some problems with correct mode configuration of the chip. As far as I understand it should be made as shown on the image. The connections I'm not sure in are marked as "?". It concerns pins 24, 25 and especially pins 26 and 27.
Here's the quotation from datasheet.
USER AND VALIDITY DATA INPUT
The user data bits in the AES-3 data stream allow for a
convenient way to transfer user-defined or application specific
data to another device containing an AES-3 receiver.
The U input (pin 27) is used in both Software and Hardware
mode to input the user data in a serial fashion. Figure 5
shows the U input timing diagram.
Validity data is used to indicate that a sample is error-free
audio data, or that the sample is defective and is not suitable
for further processing. In Software mode, the VAL bit in
control register 01H is utilized to write the validity data. In
Hardware mode, the V input (pin 26) is used to input the
validity data in serial fashion. Refer to Figure 5 for V input
timing for Hardware Mode.
When VAL or V = 0, this indicates that the audio data is valid
and suitable for further processing. When VAL or V = 1, then
the audio sample is defective and should not be used.
I don't know if any data for this pins is necessary, but I'm afraid not to connect this pins, cause it can harm DIT4096 as far as I understand.
Thanx for your replies!.
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