DIR9001 - 50ps jitter, but at what frequency ?

[percy]

Most conventional PLL spdif receivers reject jitter only above a certain frequency - typically 8Khz+. Any jitter below 8Khz would pass right through unabated.

So when they say 50ps jitter for the DIR9001, what frequency are they talking about ? Is it 50ps above 1Khz or 10Khz ?

[BrianL]

Jitter is a time domain specification which essentially measures the instantaneous deviation of a clock waveform from the ideal. For digital signals, the reference is the clock edge and for sine waves, you'd use something like the zero crossing. Jitter is usually specified in time domain units and thus does not have reference to spectral content.

If you want to look at the spectral content, then you look at a phase noise plot which will show the frequency domain makeup of the clock variation from ideal.

The DIR9001 gives only a jitter spec, not a phase noise plot.

[percy]

Actually what I am asking about is a property of the pll function of the receiver, and not that of the jitter itself. I think you are referring to the frequency of the jitter itself - for example - 2Khz of periodic jitter.
Now I am not very well versed with the pll stuff but I think I am referring to what might be known as the corner frequency or the bandwidth or loop bandwidth of the pll ?

[Iain McNeill]

50ps would be the amplitude of the jitter signal (as it were) PLL's assume that the spectrum of the jitter is white i.e. random jitter and by rejecting high frequency jitter, they bring the RMS jitter level down which is good.

But you could have harmonic jitter and that jitter would be reduced by PLL loop gain at that frequency. Its a time and frequency warp

[BFNY]

Originally posted by percy
Most conventional PLL spdif receivers reject jitter only above a certain frequency - typically 8Khz+. Any jitter below 8Khz would pass right through unabated.

So when they say 50ps jitter for the DIR9001, what frequency are they talking about ? Is it 50ps above 1Khz or 10Khz ?

Good question. I don't see it spelled out in the data sheet, the only plot shown is figure 3 on page 7, which is recovered clock jitter versus sample frequency. And the data sheet refers to the jitter as "periodic jitter, ps rms".

http://focus.ti.com/lit/ds/symlink/dir9001.pdf

But it will be directly related to the RC time constant of the PLL filter, of which the components are shown on page 15 - primary components are 680 ohm and .068uF, with a HF bypass cap of .0047uF.

As you say above, for the PLL to be able to lock on a wide range of input clock standards, it uses loop filter components that reduce the jitter reduction effectiveness below a certain frequency. The old CS8412 shows the jitter attenuation vs. frequency plot - see page 7,8 of the CS8412 DS http://www.dddac.de/files/CS8411_12.pdf

It also uses similar components for the loop filter - 1000 ohms and .047uF. If you do the math, you'll notice they both loop filters use almost the same RC time constant - about 47 and 46 usec respectively. So I would expect the dir9001 jitter rejection vs. frequency plot to be very similar to the one shown for the CS8412.

People used to play around with those values on the CS8412 to increase the RC time constant, which also increases the lock time, and decreases the wide range of frequencies over which it can lock.
That's likely a good path for DIY fun on the dir9001 as well.

[ccschua]

I hope not to introduce jitter here.

using your 1k and 0.047uF filter and the formula

1/2 pi RC, I get

3.4kHz in frequency domain of the jitter. What does this 3.4kHz mean ?

I have switched between the recommended 0.047uF to 0.01uF, I prefer to listen to the 0.047uF with 1 kohm filter.

[percy]

BFNY, thank you. Yes that is exactly what I was asking about.
Seems like other terms of describing it are Jitter Attenueation, Jitter Tolerance, and some IEC standard called IEC-60958-3.

ccschua, 47 is the time constant in µs. The frequency would be inverse of that.