Hello
I've been pondering for quite a while now, and have been searching the digital section intensively but have not found what i was looking for:
Which IC's do I have to use for splitting a cd-pro2 i2s signal at 48fs to L-/L+ R-/R+ balanced signal.
There are quite some pcb's and ciruits described for 64fs and 32fs, but not for 48fs. The overall process is the same for 48fs, but I am not able to find a simple 24-bit shift register anywhere. I've found a variable bit shift register, but this needs a circuit to set it to a 24-bit delay.
Does anybody have built such a i2s-splitter?
And I do really care for the balanced signal as I have bought two TDA1541A S2 about 6 year ago that i like to use.
Any help or suggestion is appreciated!!!
Martin
I've been pondering for quite a while now, and have been searching the digital section intensively but have not found what i was looking for:
Which IC's do I have to use for splitting a cd-pro2 i2s signal at 48fs to L-/L+ R-/R+ balanced signal.
There are quite some pcb's and ciruits described for 64fs and 32fs, but not for 48fs. The overall process is the same for 48fs, but I am not able to find a simple 24-bit shift register anywhere. I've found a variable bit shift register, but this needs a circuit to set it to a 24-bit delay.
Does anybody have built such a i2s-splitter?
And I do really care for the balanced signal as I have bought two TDA1541A S2 about 6 year ago that i like to use.
Any help or suggestion is appreciated!!!
Martin
Hi martinjufer,
I2S splitters are a bit more complicated than just using a shift register. One needs to make sure that the correct samples are combined, status of WS with respect to the delayed data is correct, and BCK has correct timing.
The principle is fairly simple, use delays for the DATA signal and select the desired delayed I2S stream (L / R) by using multiplexers (digital switches). Suitable multiplexer could be SN74HC157. This way, channels can be "ligned-up" to achieve L and R I2S streams.
For 44.1 / 16 NOS there is the CD4517 from TI (2 x 64 bits shift register with 16 bit taps). One can add 8 bit shift-registers of the same logic series for creating multiples of 24 bit delay. For higher bit clock rates use 8-bit registers like 74HC164.
I always use delayed DATA signals exclusively in order to maintain correct alighment of all derived DATA signals with respect to BCK and WS.
Depending on 32, 48, or 64 bits / frame, different delay factors are required for correct alignment.
Possible setup for L / L and R / R outputs for 48 bits / frame source:
Left channel DATA,
WS=0 > MUX for left channel DATA connects to input DATA delayed by 48
WS=1 > MUX for left channel DATA connects to input DATA delayed by 72
Right channel DATA,
WS=0 > MUX for right channel DATA connects to input DATA delayed by 24
WS=1 > MUX for right channel DATA connects to input DATA delayed by 48
This would require 1 x CD4517 (2 x 64-bit shift register with taps at 16 bits), 1 x HC157 (MUX), 3 x 74HC164 (8-bit shift register).
The 8-bit shift-registers are connected to 16 bit delay outputs to achieve multiples of 24 bit delays.
For faster splitter you would require 9 x 74HC164 to create 3 x 24 bit delay.
WS doesn't need to be inverted due to the correct delay factors, BCK might need to be inverted (fast 74HC164 registers).
It's handy to use a test track with L / R channel test in order to verify correct operation.
This splitter uses the TDA1541A in dual-mono mode, meaning both outputs of the same chip output the same channel:
Chip #1: L, L
Chip #2: R, R
This keeps the output signal fairly clean (paralleling 2 matched DACs on the same substrate) and eliminates L/R channel amplitude differences. One could even use 2 free-running DEM clocks (470pF capacitor on each TDA1541A) as each TDA1541A can be viewed as a separate converter.
The splitter could be modified by adding an inverter to one of the inputs of each MUX. This would create L, /L and R, /R for balanced mode.
I2S splitters are a bit more complicated than just using a shift register. One needs to make sure that the correct samples are combined, status of WS with respect to the delayed data is correct, and BCK has correct timing.
The principle is fairly simple, use delays for the DATA signal and select the desired delayed I2S stream (L / R) by using multiplexers (digital switches). Suitable multiplexer could be SN74HC157. This way, channels can be "ligned-up" to achieve L and R I2S streams.
For 44.1 / 16 NOS there is the CD4517 from TI (2 x 64 bits shift register with 16 bit taps). One can add 8 bit shift-registers of the same logic series for creating multiples of 24 bit delay. For higher bit clock rates use 8-bit registers like 74HC164.
I always use delayed DATA signals exclusively in order to maintain correct alighment of all derived DATA signals with respect to BCK and WS.
Depending on 32, 48, or 64 bits / frame, different delay factors are required for correct alignment.
Possible setup for L / L and R / R outputs for 48 bits / frame source:
Left channel DATA,
WS=0 > MUX for left channel DATA connects to input DATA delayed by 48
WS=1 > MUX for left channel DATA connects to input DATA delayed by 72
Right channel DATA,
WS=0 > MUX for right channel DATA connects to input DATA delayed by 24
WS=1 > MUX for right channel DATA connects to input DATA delayed by 48
This would require 1 x CD4517 (2 x 64-bit shift register with taps at 16 bits), 1 x HC157 (MUX), 3 x 74HC164 (8-bit shift register).
The 8-bit shift-registers are connected to 16 bit delay outputs to achieve multiples of 24 bit delays.
For faster splitter you would require 9 x 74HC164 to create 3 x 24 bit delay.
WS doesn't need to be inverted due to the correct delay factors, BCK might need to be inverted (fast 74HC164 registers).
It's handy to use a test track with L / R channel test in order to verify correct operation.
This splitter uses the TDA1541A in dual-mono mode, meaning both outputs of the same chip output the same channel:
Chip #1: L, L
Chip #2: R, R
This keeps the output signal fairly clean (paralleling 2 matched DACs on the same substrate) and eliminates L/R channel amplitude differences. One could even use 2 free-running DEM clocks (470pF capacitor on each TDA1541A) as each TDA1541A can be viewed as a separate converter.
The splitter could be modified by adding an inverter to one of the inputs of each MUX. This would create L, /L and R, /R for balanced mode.
Hello ecdesigns,
I saw your I2S Mono Splitter here, post # 5010:
http://www.diyaudio.com/forums/digi...e-nos-dac-using-tda1541a-501.html#post3917324
I would like to build it, but I want to use it after an SAA7220 digital filter.
How are those implemented after 4x oversampling?
All the best,
Salar
I saw your I2S Mono Splitter here, post # 5010:
http://www.diyaudio.com/forums/digi...e-nos-dac-using-tda1541a-501.html#post3917324
I would like to build it, but I want to use it after an SAA7220 digital filter.
How are those implemented after 4x oversampling?
All the best,
Salar
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