Any thoughts?
http://elecp-media.com/portal/wts/ccmcfMaPf0aqokAL6SzVbNFw6Sh
National's site:
http://www.national.com/products/catalog.do
Click on
Clock and Timing
http://elecp-media.com/portal/wts/ccmcfMaPf0aqokAL6SzVbNFw6Sh
National's site:
http://www.national.com/products/catalog.do
Click on
Clock and Timing
I didn't study the entire set of data sheets. I looked through one of them.
I think it would be hard to do what most of us would want. I would want to use a "jitter cleaner" to fix up a received SPDIF stream.
Aside from the problem of the jitter below 12KHz that the other posters have noticed, the chips have registers that need to be set to tell the chip what frequency the received clock is. You will need a micro to configure the part.
I think you would have to use one of the verious SPDIF receiver chips in software mode. Use one that will give you a status reading of the locked sample rate.
Then you will need the micro to read the SPDIF rate from the receiver and configure the jitter cleaner part for the correct sample rate. Every time the SPDIF receiver locks, the jitter cleaner will be re-configured.
The package is a 48 pin LLP, which is not DIY friendly. You will have a hard time hand-soldering this.
It sounds like a lot of development to me for a questionable amount of improvment.
I think it would be hard to do what most of us would want. I would want to use a "jitter cleaner" to fix up a received SPDIF stream.
Aside from the problem of the jitter below 12KHz that the other posters have noticed, the chips have registers that need to be set to tell the chip what frequency the received clock is. You will need a micro to configure the part.
I think you would have to use one of the verious SPDIF receiver chips in software mode. Use one that will give you a status reading of the locked sample rate.
Then you will need the micro to read the SPDIF rate from the receiver and configure the jitter cleaner part for the correct sample rate. Every time the SPDIF receiver locks, the jitter cleaner will be re-configured.
The package is a 48 pin LLP, which is not DIY friendly. You will have a hard time hand-soldering this.
It sounds like a lot of development to me for a questionable amount of improvment.
rossl said:
Take an average Input receiver like CS8412 or 14 and combine it with a decent crystal based VCXO like
http://www.tentlabs.com/Products/DACupgrades/XODAC/index.html
30dB in jitter reduction is not questionable......
best
rossl said:
Not, there's no free lunch, at least not for 209 euro, but you might like this one
http://www.grimmaudio.com/cc1grimm.htm
best
Guido Tent said:
209 euro? I can't understand why people would pay anything of the sort for a boutique clock instead of realizing if they'd only check outside the audio specialty suppliers they could find something for a fraction of the cost. Example quote I got from a manufacturer:
Fundamental: 24.576 MHz
RMS jitter 10 Hz-20 MHz: 0.25 ps (typ) 0.3 ps (max)
Phase noise at offset: 10Hz -100dB, 100Hz -130dB, 1kHz -155dB, 10kHz - 170dB, 100kHz -175dB (typ, max 3 Hz higher)
Price: $20
That's per clock for 100 quantity, about double if only 10. I was going to organize a group order on head-fi but other stuff came up (a 70 hour a week job). I'm sure other manufacturers can provide similar clocks at similar prices
It's pretty clear to me that most people seem to not realize that one doesn't have to spend ludicrous sums of money to get decent audio components. Just don't spend it with the suppliers that charge a multiple of what it's worth--shop around, going outside the circle of audiophile pawn shop masters!
muckrake said:
Well, if a cheap opamp based regulator is all that's needed to get such numbers, there is no reason to use something more expensive. Don't you agree ?
Btw, why don't everyone use such regs if they guarantee such high performance while being cheap ? Would it be that they're not that trivial to design and implement properly ? And with this PCB from Tentlabs, you're also paying for guaranteed performances, that's not diy anymore. Give 200€ to an average diyer and see how many will design a proper PLL and PS.
In any case, I don't think an opamp based regulator is used in the Tent XO-Dac. I only see one dip8 package and it's most probably used for something else (just by looking at the published schematic of a DAC to which Guido Tent contributed and that also includes a secondary PLL).
So.. do you have a gun next to you ?
PLL synth. and VCXOs
Interesting thread... I do have one ideea to use CDCL6010L as PLL synth./jitter cleaner feeded by one of many VCXOs/VCOs out there. I guess I'll use Crysteks (e.g. CVHD-950) so, let's ignore for now the interface problem...
I read in the datasheet that CDCL6010L is a preety good chip though I, somehow, "feel" (read know) that if I'll use after VCXO it will raise the jitter level at outputs. From theory, it's this a true statement or the jitter still remain in "acceptable" limits (<= 5ps)?
kind regards!
Interesting thread... I do have one ideea to use CDCL6010L as PLL synth./jitter cleaner feeded by one of many VCXOs/VCOs out there. I guess I'll use Crysteks (e.g. CVHD-950) so, let's ignore for now the interface problem...
I read in the datasheet that CDCL6010L is a preety good chip though I, somehow, "feel" (read know) that if I'll use after VCXO it will raise the jitter level at outputs. From theory, it's this a true statement or the jitter still remain in "acceptable" limits (<= 5ps)?
kind regards!
Don't know how relevant this is but I saw this somewhere:
http://www.rme-audio.com/english/techinfo/steadyclock.htm
http://www.rme-audio.com/english/techinfo/steadyclock.htm
454Casull said:
When they still express jitter in ns: Forget about it
See for a serious product here
http://www.grimmaudio.com/grimm cc1 leaflet.pdf
best
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