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Old 14th October 2008, 07:38 PM   #1
borges is offline borges  Norway
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Default Digital XO

Iain McLean and I have both been tinkering a bit with digital XOs. Here are a few notes on my system.

I have built a CD player with a custom 8x oversampler in an FPGA. The machine works with 44.1/16 input only. It's got four PCM1704 DAC chips and some special analog filters. Part of the reason for putting a custom oversampler in there is to experiment with analog topologies.

The reason for the thing to become a CD player and not just a DAC box (which I built to begin with) is that I want to provide the MCLK myself, not trust an off-board oscillator or, God forbid, an S/PDIF regenerated MCLK.

Today I have the four DACs configured to play back + and - the oversampler output. That way I have a discrete differential setup. But there's a configurable digital volume control in there so the gain options are limitless.

With a "software" update I'm able to have the FPGA act as a digital XO as well. I have a fully updateable FIR oversampler (currently 360 taps / 32 bit coefficients), but expandinding the number of FIR filters or their lengths is very feasible.

Still, for the digital XO I was planning on starting out with IIRs. After all, that's what is going on in LCR filters in speakers, anyway.

In order to move on with the XO work I'd like to get in touch with other forum members who find this interesting. I have done a fair amount of electroncis and filter design, both analog and digital. But I have never built a speaker or its XO. So I believe a tutorial or good discussion would do some good.


Cheers,
Borge
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Old 15th October 2008, 04:04 AM   #2
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Your choice to "own" the master clock is the answer to all jitter issues, I think. We have to assume that the original recording was made with a perfect clock so all focus is directed to the DAC clock. Everything in between is irrelevant right?

Or is it...
I can't find the thread where someone was positing that jitter is important on the input and output of an asynchronous SRC. I can see that if the ASRC assumes a jitter free input and output clock, and literally updates input and output at the respective clock intervals then there are problems. But the SRC4293 datasheet implies that the ASRC maintains a frequency ratio parameter that defines the output interpolation. This, if implemented well, mitigates the IO clock jitter concerns. Needs to be tested!

regarding DSP XO's:
IIR's have their advantages especially low noise in biquads. I've heard high order IIR's can get noisy though. My difficulty is I don't know of a way to compute IIR filter coefficients for filters with arbitrary phase responses independent of magnitude response. So instead, I use FIRs up to 1024taps. All you have to do is build a complex array with frequency and magnitude values and take the inverse FFT and it gives you the filter coefficients.

Because I am correcting the driver magnitude and phase to achieve an ideal acoustic response, the actual filter isn't linear phase and so it's not symmetrical. In fact the peak in the impulse is usually very close to the beginning of the impulse. So I'm not hearing the long delay and pre-ringing FIR's are usually accused of.

As for brickwalls, I think 8th order is plenty. The crossover region is about 1 octave total which is quite easy to integrate and simplifies the filter..
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Old 19th October 2008, 06:12 PM   #3
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Hi borges,

My current approach is to broadly correct the measured drive unit response with minimum-phase IIR filters (as the drivers are min-phase themselves) to give, broadly speaking, a flat response in the passband with linear phase. The crossover I then design as a separate module, which leaves me free to quickly experiment with different phase and magnitude options.

Using IIR filters only can achieve anything possible with analogue filters, is computationally cheap and has low latency.

FIR filters can get you linear-phase response and nearly arbitrary magnitude response not possible with IIR, but come at the cost of higher computational expense and higher latency. Linear phase responses also create pre-echo, which is generally regarded as undesireable even though its perceptual effect doesn't seem to have been formally evaluated.

In FIR filters, as I'm sure you know, steepness of slope and stopband attenuation are about proportional to filter length (in windowed-sinc designs, steepness and attenuation are also easily interchangeable), and long filters thus give better frequency-domain performance. However they also create more pre-echo, and the tradeoff between the two seems presently to be a matter of personal taste.

I use short linear-phase FIR filters in my own speakers. They seem to make sense to me, because I get linear-phase, perfectly-acceptable stopband attenuation, relatively gentle rolloff (I'm not a fan of super-shallow rolloff designs like first-order or anything, but using excessively sharp filters is just asking for trouble), low latency, low pre-echo and low cost.
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Old 19th October 2008, 07:41 PM   #4
borges is offline borges  Norway
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Hi Wingfeather,

what I want to do is quite similar to what you describe; linearize the driver and then put a desireable cut-off on top of that.

In my previous thread I'm suggesting some ways to make the XO IIRs that are applied after driver linearization sum to unity. This is impossible in the analog domain above the 1st order. But with digital IIR emulating analog IIR by means of bilinear transform, a lot of funny Laplace stuff can be realized. Just got to make sure it's stable.

And one thing I thought of is to recycle the denominators of the driver equivaltent equations in the XO IIRs themselves.

So the next move now is to start implementing and simulating the IIRs in FPGA. The MAC core that comes with Xilinx ISE tools go up to 32x32 bits. Which means that IIR output samples must be dithered to 32 bits before being fed back. It'll be interesting to see which of biquads and higher-order digital IIRs perform better.

Cheers,
Borge
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Old 19th October 2008, 10:06 PM   #5
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Hi borges,

Yeah, that sounds good - anything that can be transformed into the z domain will work, so you have lots of flexibility in that approach. As you said, stability is essential, but that's easy to check for.

Quote:
Originally posted by borges
Which means that IIR output samples must be dithered to 32 bits...
Be aware that you can use two multipliers in parallel to perform double-precision multiplies (will give you 96-bit results at the main adder in a DF-I topology). It's not generally necessary if you're not using using low corner frequencies (but can be if you are). If faced with the decision I'd personally go for full double-precision in biquads anyway as modern FPGAs are pretty beefy.


Quote:
Originally posted by borges
It'll be interesting to see which of biquads and higher-order digital IIRs perform better.
A useful thing is that you can build up most if not all IIR characteristics as a cascade of first- and second-order IIR sections. It's recommended to do so because making higher-order filters stable is (apparently) very difficult to do.
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Old 20th October 2008, 03:19 PM   #6
borges is offline borges  Norway
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The Xilinx FPGAs I use have a lot of 18x18 multipliers. So four of those will realize 36x36 bits.

This being _diy_ audio, I guess that a _diy_ MAC isn't out of the picture! I just wish the standard MAC that comes with the tool was a bit larger than 32x32.

But before I conclude on which type of MAC I will need, I'll play some simulations and try different rounding and dithering.

Borge
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Old 20th October 2008, 07:59 PM   #7
jahonen is offline jahonen  Finland
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I too recently experimented with hardware multipliers on the FPGA. My company whom I work for, arranged a "hobby 4-layer PCB" order (for educational purposes to make electronic design engineers more familiar with PCB design process), so I decided to realize some kind of board, where I can experiment with digital filters in FPGA.

I was quite amazed how easy it in fact was to create a working FIR-filter. The biggest difficulties were in creating working serial audio interface blocks. I guess that the simplicity was due to absence of reading those 10 cm thick user manuals for DSP processor peripherals. Just code what you really need. For HDL, I used VHDL.

Here is a picture of the board. It contains Altera Cyclone II EP2C8. Unfortunately I didn't bother to calculate the current consumption of the analog electronics very thoroughly, and thus the power supply came out somewhat underrated. My original idea was to create a testing platform for Freescale DSP56371, but since the FPGA version works so good, I have not put very much effort to bringing up the DSP.

In addition of the Altera FPGA, the board contains CS8416, CS5381 ADC, 4x PCM1793 DAC, 4x PGA2311 output gain control and MSP430F169 C for configuring/controlling the peripherals. Nothing very fancy but it "works".

Here is a sample scope screen capture where square wave is "decomposed" into various frequency bands. Channel 1 is the input, channels 2 thru 4 are the outputs. Nice phase-linear outputs. Small nonsymmetricies are due to the generator used to feed the board.

This board is just a platform for testing. I intend to create something more fancy in the future, as I get a clear picture what I really want. Maybe EP3C40 for the FPGA, or something like "per-speaker" scalable DSP-board linked with some kind of fiber-optic links. This clearly needs some system design.

Regards,
Janne
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Old 21st October 2008, 05:59 AM   #8
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Nice board Janne. From what you describe it is a very well equipped device and capable of excellent sound.

I am using an Analog Devices Blackfin devkit right now with an AD1836 2in-6out codec. I'm using 16bit input at 48KS/s with 16 bit coefficients and a 40bit MAC. With careful gain management through the code I'm getting 80dB dynamic range 'A' weighted. Doesn't look too good on paper but it sounds very nice. You may be worrying needlessly.

I think the important stuff is in the choice of target response and the method of calculating filter coefficients. The actual implementation is secondary and has multiple pros/cons/compromises which average out as far as I can see.

My choice of target response is 20Hz - 20KHz flat magnitude and phase in the acoustic domain. From there I apply an 8th order Linkwitz-Riley filter prototype (again with flat phase response to guarantee drivers are in phase throughout the crossover range) and subtract the driver acoustic measured magnitude and phase (and also amplifier if it's not good enough) That provides the filter response needed to get a perfect acoustic response from that driver. (and one that is impossible in analog

With all corrections rolled into one, I use the inverse FFT method to create coefficients. I do this in MATLAB because I find it to be the most complete mathematic playground. (OK, it's ability to handle HUGE arrays and the graphing tools are unbeatable)

So my questions to you guys would be: what target responses are you aiming for, and how do you calculate your coefficients?

Borges: on dither. Surely you only need to apply dither at the last truncation, not every truncation? Did I read that wrong? Or is this a technique to mitigate noise in IIRs?
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Old 21st October 2008, 09:07 AM   #9
borges is offline borges  Norway
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Quote:
Originally posted by jahonen
... 4x PGA2311 output gain control
Janne, your board looks great for your purpose. Just a suggestion if you target hi-end analog: skip the PGA2311. I had one in a previous version of my DAC. In listening tests everything was OK running the PGA2311 at 0dB and using an external preamp. But when we turned the PGA2311 down to -30dB-ish to talk directly to the power amp, the sound became much duller than with the analog pre. I believe it's down to the feedback structure of teh PGA2311.


Quote:
Originally posted by Iain McNeill
So my questions to you guys would be: what target responses are you aiming for, and how do you calculate your coefficients?

Borges: on dither. Surely you only need to apply dither at the last truncation, not every truncation? Did I read that wrong? Or is this a technique to mitigate noise in IIRs?

Iain, on the 1st question: Don't know! My problem is that I have never worked much with speakers. So I'm eager to learn more about clasical XO design and how to deal with speakers in the Laplace domain.

On the second question, the MAC in the tool performs 32x32 bit multiplication. With both inputs signed, that should give signed 63 bit accumulator output. And those 63 bits I'm going to dither down to 32 in a single quantization before feeding the data back inside the IIR built around the MAC.

In my digital volume control (which I put in for the heck of it and which probably performs worse than the PGA2311 at gain!=0dB) I quantize once more and dither to the 24-bit level of the DACs.

I did consider the IIR feedback to be the exact output that I fed to the DACs, and hence do a bit of noise shaping. Maybe I'll go down that road later. For now I guess that feeding back 32 bits and then quantize again for the 24-bit DAC is better than feeding back the 24-bit DAC signal. But I may very well be wrong here.

The purpose of dither is to reduce harmonic distortion when you quantize a signal (be it digital or analog). Adding a small portion of uncorrelated noise will chop the harmonic spikes. So yes: whenever I'm throwing away LSBs I apply as many bits of dither.

Well, when I'm throwing away a LOT of LSBs I only apply 32 bits of dither to the most significant of the dumped LSBs.

Borge
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Old 23rd October 2008, 01:37 PM   #10
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Quote:
Originally posted by borges
For now I guess that feeding back 32 bits and then quantize again for the 24-bit DAC is better than feeding back the 24-bit DAC signal. But I may very well be wrong here.
Nope, that's the right thing to do. It's detrimental to use less bits for the feedback than is possible, because the quantisation noise is generally boosted by the feedback loop. You want to minimise it in the first instance by using as many bits as possible. Flat 24-bit performance can't ever be achieved with 24-bit feedback for this reason. It can sometimes be achieved with 32-bit feedback, if the cutoff frequency is high enough (maybe 1kHz or more at 44.1kHz, I can't remember offhand). If you want guaranteed 24-bit performance with cutoffs down towards the bottom of the audio range, you'll need to bite the bullet and use double precision for the feedback. One thing to note is that while double-precision obviously increases computational complexity of the filter, it does essentially remove the need for dither in the quantiser. Will save a few cycles/gates.

Only in such an excessive case as a 64-bit quantisation would I not use dither; I would dither every quantisation to 32 bits or less. Flat TPDF dither is my preference.

Quote:
Originally posted by borges
[B]I did consider the IIR feedback to be the exact output that I fed to the DACs, and hence do a bit of noise shaping.[/I]
Hmm, nice idea in theory - I think you'd have a hell of time getting a useful noise-shaping characteristic out of the biquad's poles though!
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