Real or fake PCM63?

[Bernhard]

Originally posted by PA0SU


The digital filter, oh yes, but you also need it in a NONOS-system!

I have to have another look at my DAC if there might be such a filter.

Originally posted by PA0SU
Both, the PCM56 as the PCM63 do have a current output [of some 4 mA] and do not accept a voltage larger than a few mV at their outputs for linear operation. This means that the resistance at their outputs should be smaller than a few ohms.

PCM56 is very comfortable with 500mV @ 500ohm / 1mA

Originally posted by PA0SU

This means that noise comes in sight when you do not use a special amp (like an LT1028) so why should you not use a very linear low noise op amp IV with zero ohm (< 1 ohm) input resistance? Try the OPA134.............

Not much to amplify here, I use the +6dB TVC to convert from +/- 250mV balanced to 1V SE.
No opamps.


All your mentioned drawbacks apply to real or fake PCM63, that are some of the reasons why I do not use it.

[PA0SU]

Originally posted by Bernhard

Not much to amplify here, I use the +6dB TVC to convert from +/- 250mV balanced to 1V SE.
No opamps.

All your mentioned drawbacks apply to real or fake PCM63, that are some of the reasons why I do not use it.

Okay, be happy with it. I never understand the objections against op amps....
BTW (a stupid question) what is a 'TVC'?

[finneybear]

Originally posted by spzzzzkt
Finney,

I'm following roughly what Jos has sketched out: PIC -> 16bit serial dac -> Tent VCXO. I'm basically at the stage where I've got the PIC talking to the DAC via SPI, and have the comparator and PI loop running. The PI loop constants need tuning to get it to stabilize properly. When I posted earlier I'd been having some trouble with the SPI communication, but I have that sorted now.

cheers
Paul

Paul,

The missing link is the FIFO. FIFO acts like cushion so your XO tuning will be less proactive. The clock signal in SPDIF usually contains long term shift and short term jitter. FIFO is good to mask out the short term jitter, i.e. spurious noise around the main frequency. Definitely your XO tuning should not react to this, instead, it shall focus on the long term frequency shift.

Another good thing about FIFO is that you can easily figure out the clock shift trend through FIFO's status signals such as 'almost full', 'almost empty', etc, something very hard to do with the simple PIC structure. And remember PIC is a big jitter source itself! Without FIFO, PIC's own jitter will play into the game of judging the SPDIF clock shift.

If the XO tuning circuit were too proactive, you are not reducing the jitter, instead, you are just making things worse! You always have to keep this in mind.

As I have talked about before, the main challenge is still the PIC-DAC-VCXO loop. How linear will the DAC outout be? How accurate is the output voltage? How noisy is it? How will XO react to voltage change? How linear will it be? How will XO behave during voltage change? This loop is tricky to do and can be very expensive to do it right.

This is why people would simply use DDS to replace this loop. They also use FPGA because you can have controller and FIFO put in together. The only down side is that a top DDS chip can easily cost $50+. It also needs a XO running as high as 50-100MHz.

The FIFO/DDS thing usually takes a full month of work for an engineer so dont feel frustrated. Whatever problems you have run into are exactly what others have encountered. It does need some serious work.

My suggestion will be simply ditch this SPDIF thing. Check out this nice I2S solution. And yes, it is available now! Interested?

[finneybear]

Originally posted by irgendjemand


Finney,

There is something about "Removing CD drive jitter via buffering" on http://www.hydrogenaudio.org/forums/...howtopic=54297

Isn't your above mentioned solution (in the Transport) goes the same direction that Genesis Technologies went with its Digital Lens, build by Paul McGowan, in 1996?

Putting it in the Transport (or just behind it), you get to the same problem as described in the Stereophile review
http://www.stereophile.com/digitalprocessors/824/

IJ.

That digital lens thing is a very dumb FIFO solution. Only good for remove some jitters yet cant handle long term frequency shift. Again, an antique techique trying to solve a problem in the wrong way!

There are lots of misunderstandings about receiver chips such as CS8420 and DIR9001. As far as clock recovery goes, DIR9001 is as good as it can be. The add-on jitter is only extra 100ps. The real problem is the signal quality of the input SPDIF. If the signal isnt clean, DIR9001 will not be able to do magic for you. If the signal is relatively stable, DIR9001 will only add extra 100ps jitter above it. So the scenario comes to:

1. The SPDIF signal is clean, DIR9001 will do a job good enough. An extra simple reclocking device may actually get things worse than do any good.

2. The SPDIF signal is bad, DIR9001 will get you lousy output yet a simple reclock device will not be able to pull things back together either.

In other words, if you cant do reclocking right, it will be better off that you pay attention to the SPDIF source instead of wasting time on the DAC.

This is the same with a system with word clock. The DAC part is fair straightforward yet it's very hard to get the transport synch to the word clock correctly.

[finneybear]

Originally posted by regal
You could use a 74ct9046A PLL- VXCO to SRC before the SM5842.
That is if you don't want to be a pioneer with the buffer, could be a long and expensive ordeal.

Here is a diagram:

http://www.hagtech.com/pdf/hagdac.pdf

Gosh, that PLL thing is a major jitter source itself already! And it's even a 5V device! How much propagation delay are we expecting?

[finneybear]

Originally posted by tritosine
simple, bypass the spdif receiver so the digital filter gets the i2s straight. Btw Finney also hinted something about a new transport with dsp onboard , can even bypass the digital filter then, sounds cool ? Anyway wadia has DSP upsampling since 80's, this might also "contribute something".

The beauty of HDD player is that you can do 16/44 to 24/192 upsampling on your PC first with tools such as SSRC. You can try as many combinations, as many different parameters as you want to get the best upsampling result before you send the wave files to the player. No more involvement of digital filter. No more bad side effect of ASRC either.

Sure, if the DSP had extra power, you can build your own upsampling function in firmware as well.

[finneybear]

Originally posted by PA0SU


This is all rubish, Rubish, RUBISH, RUBISH. Evary CD-player has already a FIFO. The only important thing is to use a low jitter clock to move the data from this FIFO.

Nope, nope, you even dont know which FIFO I was talking about. Reading data out of a FIFO? What if the FIFO is empty already? Your reclocking circuit is smart enough to fill in music data automatically?

[finneybear]

Originally posted by PA0SU
This is my best solution:

Again, an antique solution trying to solve the problem in the wrong way! Hehe

[finneybear]

Originally posted by PA0SU


Yes he does. This piece you quoted is only an introduction to why a VCXO+PLL should be used.

See, you have got it totally wrong. The key is the FIFO. You even do not need a VCXO+PLL. You can do it with a DDS with a much better result!

As for the FIFO/DDS thing, you can put it anywhere, before receiver, after receiver, after digital filter, etc. These are just minor implementation differences. Some people feel clock into the digital filter should be low jitter already, some believe it should be the DAC chip. That's it.

[finneybear]

Originally posted by Bernhard


PCM56 is very comfortable with 500mV @ 500ohm / 1mA

I totally agree with this. PCM56 is what I call the last, truely bi-polar DAC by BB/TI. It has an excellent 1.2Kohm current output impedance, a relatively long settling time. This means PCM56 can live happily with good OPs.

PCM63 starts to get worse with a 670ohm output impedance then PCM1704 basically is a nightmare.

This is why I really like ADI chips. They in general have better output current source. We had planned to mount D1V3 with AD1862, and still want to...