Just request one from ESS. You need to sign a non-disclosure agreement, but it's still pretty easy.
Hi
Just write to this address: bryans@shawelectronics.com
You do not need to sign any non-disclosure agreement. The ESS has cancelled the confidentially status on this document from a years ago or so...
I personally experienced no answer ever from ESS at my inquiry on this subject..
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DSD playing mechanism in Sabre32 architecture
I like the sound characteristic of DSD256 the best among input signal formats compatible to Sabre32.
In the case of TI PCM/DSD179x DAC chips of "Advanced Segments" architecture, they say "only an analog FIR is applied to DSD input signals."
On the other hand, how is a raw DSD input proceesed in our Sabre32 DAC chip?
Has anyone read or heard technical details of DSD signal processing in the chip?
My guess is;
As Sabre32 has 6 bit multilevel DA conversion units for Delta-Sigma modulation, a raw DSD 1 bit Delta-Sigma modulated signal might be decimated to 6 bit Delta-Sigma modulated signal through a FIR stage internally.
I like the sound characteristic of DSD256 the best among input signal formats compatible to Sabre32.
In the case of TI PCM/DSD179x DAC chips of "Advanced Segments" architecture, they say "only an analog FIR is applied to DSD input signals."
On the other hand, how is a raw DSD input proceesed in our Sabre32 DAC chip?
Has anyone read or heard technical details of DSD signal processing in the chip?
My guess is;
As Sabre32 has 6 bit multilevel DA conversion units for Delta-Sigma modulation, a raw DSD 1 bit Delta-Sigma modulated signal might be decimated to 6 bit Delta-Sigma modulated signal through a FIR stage internally.
DSD512 Play with a synchronous master clocking
These days, I have been trying a play of DSD512 sources on ES9018 (TPA Buffalo II) with a synchronous master clocking of 90.3168/98.304MHz. However, the playing is very unstable and suffering a burst of DSD specific noises.
Does anyone establish a stable play of DSD512 with a 90MHz synchronous master clocking?
These days, I have been trying a play of DSD512 sources on ES9018 (TPA Buffalo II) with a synchronous master clocking of 90.3168/98.304MHz. However, the playing is very unstable and suffering a burst of DSD specific noises.
Does anyone establish a stable play of DSD512 with a 90MHz synchronous master clocking?
Shall I presume that inverted I2S signals would have the same efect as inverted MCLK?
I intend to design a dual clock board based on CCHD975 oscilators (45.1584 MHz and 49.152 MHz) and feed the BIII directly from them and SDtrans after an D flip-folp configurated as divider by 2. SDtrans will command which clock is required to run based on the played file sample rate.
It will be very easy to take the clock for SDtrans from inverted Q or non inverted Q therefore all the i2S signals will be inverted or non inverted in rapport with DAC's MCLK
Oscillator belongs to the dac, as near as possible. Better to slave the transport. I am looking for a way to slave my transport as well:
I use a lampizator modyfied Denon. it has several clocks, generated by a 27Mhz Quartz and a PLL chip. So I am in need of a 108Mhz Oscillator, which I have not seen yet.
Did I said something else? The dual oscillator board will be integrated with the DAC, very close to Sabre chip, and MCLK frequency will be commanded by the transport, SDtrans in my case, therefore the BIII DAC will be in sync mode.
Send a PM with your address and I will send you a 1ps jitter 108MHz oscillator.
@rolls did obviously not want / need the oscillator, but I got PM from others.
As I have a limited supply I send the requests I have received until now.
These oscillators are custom specified and custom built (like the 22.5792/24.576M, 90.3168/98.304M etc. I also had custom built) with all specifications improved...
So far none of the requesters wanted the oscillators..
Maybe they believed this was a sales campaign
However I saved the stamps on some letters..
Timing control within ES9018
I believe many of DIY ES9018 users have experienced a positive effect of "synchronous master clocking" scheme on resultant sound quality. I use the term, "synchronous master clocking" as "providing a master clock which is synchronous to BCLK of I2S or DSDCLK of DSD, of which frequencies are x 256, x 512, x 1024, x 2048 of fs.
I have thought why the method is better than an asynchronous master clocking for a long time. I'd like to explain my considerations on a series of posts and to request your frank comments.
My basic position is a strong supporter of ES9018 DAC architecture that performs the best, I believe, among commercial DAC chips easily available in the market.
First, here are my FAQs, questions and answers.
<FAQ>
Q1. Is there any explicit register setting that switches a clocking from "asynchronous" to "synchronous"?
A1. No. ES9018 does not care whether its master clock is synchronous or asynchronous.
Q2. What does "DPLL" in ES9018 mean?
A2. No common users exactly know any true meaning of the term "DPLL".
Q3. Is there any explicit register setting that turn DPLL OFF?
A3. No. DPLL is always ON even if a synchronous master clock is provided.
Q4. What does "Jitter Reduction" functionality in ES9018 mean?
A4. No common users exactly know any true meaning of the term "Jitter Reduction" neither.
Q5. Does ES9018 have any internal built-in analog or digital oscillators?
A5. Its answer might be "No".
I believe many of DIY ES9018 users have experienced a positive effect of "synchronous master clocking" scheme on resultant sound quality. I use the term, "synchronous master clocking" as "providing a master clock which is synchronous to BCLK of I2S or DSDCLK of DSD, of which frequencies are x 256, x 512, x 1024, x 2048 of fs.
I have thought why the method is better than an asynchronous master clocking for a long time. I'd like to explain my considerations on a series of posts and to request your frank comments.
My basic position is a strong supporter of ES9018 DAC architecture that performs the best, I believe, among commercial DAC chips easily available in the market.
First, here are my FAQs, questions and answers.
<FAQ>
Q1. Is there any explicit register setting that switches a clocking from "asynchronous" to "synchronous"?
A1. No. ES9018 does not care whether its master clock is synchronous or asynchronous.
Q2. What does "DPLL" in ES9018 mean?
A2. No common users exactly know any true meaning of the term "DPLL".
Q3. Is there any explicit register setting that turn DPLL OFF?
A3. No. DPLL is always ON even if a synchronous master clock is provided.
Q4. What does "Jitter Reduction" functionality in ES9018 mean?
A4. No common users exactly know any true meaning of the term "Jitter Reduction" neither.
Q5. Does ES9018 have any internal built-in analog or digital oscillators?
A5. Its answer might be "No".
I have for some time fiddled with a dual mono ES9018 with synchronous clocking at 22.5792MHz and 24.567MHz...
With the custom setup and register programming I have implemented there are 0 - zero dropouts or any of the problems I have registered most / many DIY setups have playing PCM 44.1k/16bit to 384k/32bit, DSD64 and DSD128, and SPDIF up to 192k/24bit.
Also DSD256 and DSD512 should work with these "low" master clock frequencies, but I have not tested.
The clocks will soon be changed to 90.3168MHz and 98.304MHz, but there have been quite some fun to get flawless performance with the 22.5792MHz and 24.567MHz clocks.
I have also compared PCM with DSD (identical sources) and must thus demystify the rumors "an unverified account or explanation of events circulating from person to person and pertaining to an object, event, or issue in public concern" stating that DSD plays better than PCM.
These rumors may be true when a 16 or 24bit PCM source are compared to DSD using a ES9018 DAC, but untrue when a 32bit PCM source are compared to DSD on a ES9018 DAC. For DACs with 24 or 16bit limitations (processing) the results may also favor PCM with 24 and 16bit PCM sources.
And - yes DSD sounds (much) better than a 16 or 24bit PCM source on the ES9018 - DSD even better than a original DXD 352.8k/24bit master. But a 32bit PCM source (without dither and "advanced" filtering) beats DSD with a good margin.
The test environment have not been using my Linux based music server, but a MacBook Pro (quad core i7, 16GB RAM, SSD) with OSX 10.8.2 and Audirvana Plus 1.4.1 - as this have only been a "debug" setup to optimize the USB adapter and DAC functions...
OSX 10.8.2 are "tweaked" by removing some kexts that slowed the overall performance etc..
Total CPU load when playing 352.8k/32bit or DSD128 are thus below 1%....
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