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Old 22nd April 2008, 01:47 PM   #491
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Join Date: May 2001
Location: London UK
Quote:
Originally posted by Russ White


Did you make sure you have the transceiver setup for the correct PCM format? Is it I2s, LJ, RJ? 24 bit 16bit?

Please reply in the support forum.
I2S was set up correctly as per instructions. I did post in the support forum but no response except I got sent an Ott Board.

Thank you Twisted Pear!

Fred
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Old 22nd April 2008, 02:59 PM   #492
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Quote:
Originally posted by Russ White


I think that's been established, ASRC would be there, but would not be doing much to correct things if they are already correct.

Interestingly, there is a register to disable "jitter correction" but I am not sure exactly what this implies for the data.

Cheers!
Russ

"disable jitter rejection" will simply shut the correction engine off and therefore should ONLY ever be used with a synchronus (phase alligned, not just the same frequency derived from another source) mclk. So basically, it will revert to the same way every other DAC out there does it if you dont like the asynchronus way Martin/I proprosed. If you still want to try the Sabre but already feel you have a extremely well done transport with low phase noise clock then this option might be for you. I would be very interested to see someone do this and compare the sound. ie, comapre the sound of

1. Sabre in snynchronus mde, with very high end transport with low jitter mclk.

2. Crappy transport full of jitter, then let the Sabre do its thing.


From a mathematical point of view, the Sabre will start to attenuate the jitter at around 0.1Hz or so, so I would like to see this comparison done.


Thanks

Dustin



Ohh, by the way, I saw someone asked if you can monoblock. You can do this, and then tie all 8 cahnnels together into 1 I/V stage, however it would require some exturnal coding to get the same data on both channels in the I2S/LJ/RJ serial source. THere is no option to set a register in teh chip to wire it all together. You guys just keep thinking of using it in ways I didn't Which is really good.
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Old 22nd April 2008, 03:42 PM   #493
peufeu is offline peufeu  France
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Quote:
I would be very interested to see someone do this and compare the sound. ie, comapre the sound of

1. Sabre in snynchronus mode, with very high end transport with low jitter mclk.

2. Crappy transport full of jitter, then let the Sabre do its thing.
Of course you realize that case 1 is not possible if SPDIF is used ?
The options that are OK in my book are :

Option A - Low jitter Master clock in DAC, feeding DAC directly, source slaved to this clock.
I have slaved :

- a CD player (worked well but the player died, I had overlooked the fact that CD723 if not receiving a clock will bug, smash repeatedly the lens into the disc 10 times per second, and shortly expire, well no big loss, it sucked anyway),

- an RME soundcard (worked a lot better, since you can use Amarok and store 1000 CDs as FLAC on RAID5, so convenient). This one was extremely easy, I encoded a silent SPDIF containing only the Master Clock, fed this to the RME, the "Lock" LED lights on the soundcard, and that's it, it's synchronous. Looking on the scope, it's very easy to see, trigger the scope on WordClock coming out of the SPDIF receiver and display WC on one trace, Master clock on the other, plug the clock link in the soundcard, and both traces freeze. CS8412 working in double-buffer mode means you have no worries about clock phase.

- an Ethernet FPGA module with packetized audio transfer from a Linux PC, using UDP, works well, receives clock from DAC, outputs IS. Version 2 is in the works. The nice thing is, you have 100 Mbps at your disposal, channels, sample rate and bits per sample are your choice. Wether you process signals in the PC or the FPGA, your choice.

Option B - Receive SPDIF from transport, use a local VCXO to derive clock, using a suitable low-jitter PLL scheme. Analog PLLs are tricky, AFAIK only Tent succeeded. Digital PLLs with a FIFO and a uc seem to be easier. V2 of the FPGA module will have that feature.

A clock that has been SPDIF-encoded, or a clock that has travelled in a feet of flat cable with data signals and a shared ground, will not give good sound quality. LVDS over twisted pair could make it work, but why bother ? Either be incompatible and put the clock in the DAC, or be compatible and use a proper clock recovery (ie VCXO PLL).

Now, if the Sabre has an ASRC that is as good as it seems to be, things could get simplified, just give the Sabre a good clock and let it handle the rest.

I would like to test that.

I am making a modular DAC platform with the FPGA module (with Ethernet, SDRAM, and lots of IO), a baseboard with lots of digital audio IO (SPDIF, ADAT, wordclock, etc, clock in, clock out, optical, twisted pair, etc), a module with the local clock (XO or VCXO) and associated logic, and then plug-ins for DACs, IV and outputs. I took excruciating care of the layout and sensitive signal paths. The hardest part was the FPGA module, the PCBs will be sent for fabrication this week, after that, in a couple months it should be wrapped up.

This will be an open project, I want several people to participate in development (JACK driver, foobar driver, filters, GUI, etc) and in evaluation (listening to various DACs and exchanging modules, etc). I would like to include the Sabre in there, too.
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Old 22nd April 2008, 04:33 PM   #494
hirez69 is offline hirez69  Europe
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Quote:
Originally posted by dpaws
For WMS:

Hi + thanks for your posts. I'm extremely interested in a passive I/V transformer coupled output stage for the Buffalo. I'd be grateful if you could keep us (well, me at least) posted on your findings with a schematic and component values when available.

Very much appreciated, Steve

That would be very useful for me!
Thanks WMS and Steve.

hirez69
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Old 22nd April 2008, 04:47 PM   #495
4real is offline 4real  Netherlands
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I found some datasheets and pinouts, and things are looking much clearer now Great stuff.

One thing I have not found. De stopband attenuation is specified, but what about passband ripple? How small is it?
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Old 22nd April 2008, 04:57 PM   #496
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Quote:
Originally posted by 4real
I found some datasheets and pinouts, and things are looking much clearer now Great stuff.

One thing I have not found. De stopband attenuation is specified, but what about passband ripple? How small is it?

0.005
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Old 22nd April 2008, 05:07 PM   #497
4real is offline 4real  Netherlands
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Okay. That's actually not extremely low. Is there a reason for this? Other high-end dac's having such a deed stopband have far less bandpass ripple. How about pre-echo?
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Old 22nd April 2008, 07:10 PM   #498
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Quote:
Originally posted by 4real
Okay. That's actually not extremely low. Is there a reason for this? Other high-end dac's having such a deed stopband have far less bandpass ripple. How about pre-echo?

By pre-echo I assume you mean the begining the the impulse responce of the filter before the main "lobe" I guess it could be called. The impulse responce is almost symmetrical due to the fact the there is an FIR and IIR filters in the path. The reason for only 0.005dB is that I wanted 120dB image rejection, and with the amount of taps in the filter, that is what you get.


Thanks

Dustin
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Old 22nd April 2008, 07:23 PM   #499
4real is offline 4real  Netherlands
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Surely it is symmetrical, but that does not mean that there is no pre-echo. As far as I know passband ripple is directly correlated tot the magnitude of the pre-echo, and therefore a smaller ripple will give you less pre-echo. I Could be wrong there of course...
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Old 22nd April 2008, 08:18 PM   #500
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Quote:
Originally posted by dusfor99

Ohh, by the way, I saw someone asked if you can monoblock. You can do this, and then tie all 8 cahnnels together into 1 I/V stage, however it would require some exturnal coding to get the same data on both channels in the I2S/LJ/RJ serial source. THere is no option to set a register in teh chip to wire it all together. You guys just keep thinking of using it in ways I didn't Which is really good.
Indeed, althought it may be a small number outside of DIYland, there is likely interest in interfacing the output of a DF such as the PMD-100 or PMD-200. The thought of HDCD feeding the Sabre is a facet of what got my attention. In fact, the way this thread has many of us salivating, you would think there are some fleshy curves somewhere, but that is OT, and I don't operating theta. The PMD-100 would need glue logic either HW or SW to interleave it's output, but the PMD-200 appears to have an interleaved output mode available when in SW mode, and could interface 24/176 or 24/192 directly to the Sabre in it's current incarnation.

What may be a slightly larger piece of the market share is high end dual mono. Maybe that would carry some weight with the friendly suits across the aisle in Sales and Marketing.

Regardless, when you bump a rev on the chip to add input auto select in standalone mode, would you consider also adding a mono input mode to the mix...? I know that may be a bit much, as it not likely that could be done metal mask only, but the suggestion had to be placed.

Cheers,

WMS
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