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Old 21st April 2008, 06:53 PM   #481
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Quote:
Originally posted by fmak


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I am not sure Pics will help as the source is a satellite receiver with the AK4351. The following may help you make an assessment.

AK4351 LRCK 48 kHz 1.6Vdc bias; BICK around 2.8 MHz 1.6Vdc; SDATA typical eye pattern signal 1.6Vdc; MCLK 12.2896 MHz around 1Vdc.

I coupled these to the Twisted Pear board LRCK, BCLK, DIn with and without blocking cap, MCLK and all I get is noise from the AK analog output and silence from the 8804 spdif output. For some reason my external dac indicates lock on at quad speed (??). The WM PCM input terminals have similar dc biases with no signal input and therefore I assumed that it was ok to couple. Anyway there has been no damage.

Would apprecaite your help

Either I have made a mistake or there is a timing issue?

Fred
Did you make sure you have the transceiver setup for the correct PCM format? Is it I2s, LJ, RJ? 24 bit 16bit?

Please reply in the support forum.
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Old 21st April 2008, 09:53 PM   #482
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Quote:
Originally posted by peufeu
No, I don't know what's in the Saber board, but I would like to find out. When my DAC test platform is done I definitely plan to include the Sabre in the list of its victims.

Also about the price of this Audiopraise gizmo : I would calculate amortization of 1 month of designer time over the number of sold gizmos ; if they sell 50 the price is justified, if they sell 1000, well...

Question for Dustin :

So, the Sabre has an ASRC in it.
What happens if I use the same clock in the data input and in the low jitter clock input ?

Clarification :

Suppose I have a source of digital audio data which can either run on its own clock or accept an external clock (this can be a transport, soundcard, whatever).

I input the digital audio data from this source in the Sabre.

Now, if I make the source use the DAC's internal clock (the one the Sabre uses for its low-jitter circuits), the ASRC becomes useless then.

So, what does the Sabre do ? Does it still use the ASRC, or does it just use a FIFO ?

1 month? Man I wish I could do it that fast.

If you use the same clock, then your right the ASRC is renedered useless by definition. It simply doesn't do any corrections to the datastream. There is no "FIFO" in this asrc.

Thanks

Dustin

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Old 21st April 2008, 11:37 PM   #483
NeoY2k is offline NeoY2k  France
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to peufeu:
Just stop me if I'm wrong, but even if you clock the source from the clean clock inside the DAC, you may still get jitter: how well does the source clocks its output from the incoming clock? And there may still be a little bit of jitter from the cable or fiber used.

So ASRC may not be very usefull, but may help reduce any residual jitter?

I asked myself a similar question: what if I want to use a wordclock. Looks like a waste or time with this DAC.

Anyway, the device I have in mind will have WC input and output (from the TC dice chip) so why not wire it...
Just finished reading the 350 pages datasheet of this chip. Not everything is clear... Why can't everybody write as good datasheets as Analog Devices or Wolfson :'( .

I just asked ESS for the datasheet as it doesn't appears to be online anymore. I hope it will be well done
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Old 22nd April 2008, 12:02 AM   #484
KSTR is offline KSTR  Germany
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A DS marked "confidental advance information" I managed to get, with some hints in this thread, somewhere. Same for the demo board schematic...

The DS ist not that complete as one wants it to be... thus the many additional breadcrumbs from the designer in this thread...

To Russ and all the other contributers to this project: Two thumbs up! This thingie really seems to be the DAC of choice, could become a DIYA reference project.

- Klaus
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Old 22nd April 2008, 12:32 AM   #485
peufeu is online now peufeu  France
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Quote:
Originally posted by NeoY2k
to peufeu:
Just stop me if I'm wrong, but even if you clock the source from the clean clock inside the DAC, you may still get jitter: how well does the source clocks its output from the incoming clock? And there may still be a little bit of jitter from the cable or fiber used.
Ah, well, of course, anything that is recovered from SPDIF is full of jitter anyway. That's why you reclock with a few D latches (on multibit DACs) or you feed the DAC a clean clock on its MCK (for sigma delta's).

Note that a clean clock can be a XO in the DAC to which the transport is slaved, or a cleanly recovered clock from SPDIF, a la Tent (analog PLL), or with a digital PLL. As long as the clock and the data source are synchronous, you don't need an ASRC... so I'm wondering what the ESS DAC would do in such a situation, still use the ASRC or not ?
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Old 22nd April 2008, 12:37 AM   #486
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Quote:
Originally posted by peufeu
. so I'm wondering what the ESS DAC would do in such a situation, still use the ASRC or not ?
I think that's been established, ASRC would be there, but would not be doing much to correct things if they are already correct.

Interestingly, there is a register to disable "jitter correction" but I am not sure exactly what this implies for the data.

Cheers!
Russ
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Old 22nd April 2008, 12:41 AM   #487
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Quote:
Originally posted by KSTR
To Russ and all the other contributers to this project: Two thumbs up! This thingie really seems to be the DAC of choice, could become a DIYA reference project.

- Klaus
Thanks Klaus,

I have been listening to Buffalo for many hours now. I can say I would not be surprised the Sabre chip was to be the new benchmark DAC.

I have to say I would have never imagined this chip coming from ESS, but Dustin and Co.have a real winner on their hands.

My hope is that it becomes a bit more available to DIY folks. That is that they can buy say one or two chips, not just qty >= 5.

Cheers!
Russ
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Old 22nd April 2008, 03:12 AM   #488
dpaws is offline dpaws  United Kingdom
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For WMS:

Hi + thanks for your posts. I'm extremely interested in a passive I/V transformer coupled output stage for the Buffalo. I'd be grateful if you could keep us (well, me at least) posted on your findings with a schematic and component values when available.

Very much appreciated, Steve
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Old 22nd April 2008, 04:23 AM   #489
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HI Russ White,
Can I know when Buffalo is available for DIYer?
Can I build monoblock version?
Cheer
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Old 22nd April 2008, 11:00 AM   #490
NeoY2k is offline NeoY2k  France
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Peufeu: I'm not that sure that recovering a MCLK from a wordclock derivated from the DAC to clock the transport will give better results that having a cleanly clocked source and let the Sabre do the reclocking. PLLs are so far from perfect... (even 4th order ones).

Anyway, as I'll use a Dice chip, i'll have wordclock in/out and masterclock in/out, so I'll be able to experiment quite a lot. But the Dice board will be quite hard I think...

I have to start by designing my own eval board for it (1500$ the eval board is a joke. I'll make a simple board and connectors for wrapping stuff around it).

But the DAC board is for within two weeks!

- The DAC board itself, with regulators for the digital and the analog part. i2s and i2c on a connector.

I still have questions on ground planes decoupling between AGND and DGND.

- The XO board (with it's own regulators, just plugs near the DAC).

- The power supply board

- The IV board (plugs at the end of the DAC board) with it's own regulators for each channel, and relays for switching outputs between 8 channels mode and 2 channels mode.

This gives me high connectivity and easy debugging (and higher PCB costs, sic). Just: I know wires have to be kept short from the output of the dac to the IV stage, is it still ok to have plugs or relays on it?

Thank you
Nicolas
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