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Old 14th February 2008, 02:44 PM   #31
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Old 14th February 2008, 09:06 PM   #32
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Hi All,


Here is a link to the website, some more data has been posted here, but its still a work in progress.

http://www.esstech.com/techsupp/drivers.shtm
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Old 15th February 2008, 09:26 AM   #33
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Quote:
Originally posted by dusfor99
Hi All,


Here is a link to the website, some more data has been posted here, but its still a work in progress.

http://www.esstech.com/techsupp/drivers.shtm

I have to say, that is a pretty complete collection of stuff there - far better than a basic data sheet. You guys really have considered pretty much everything!
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Old 15th February 2008, 01:21 PM   #34
rossl is offline rossl  United States
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Quote:
Originally posted by dusfor99
Hi All,


Here is a link to the website, some more data has been posted here, but its still a work in progress.

http://www.esstech.com/techsupp/drivers.shtm

Hi Dustin,

Glad to see all that information is up on the web site.

I wonder if you could clarify something. I have only tried stereo SPDIF on the demo board. But I'm still a little confused.

The White paper mentions setting the part into stereo mode and 8 channel mode. But the white paper and the data sheet are not really clear on the mode setting. How did you do that?

There may be something in the docs that I missed. Looking through the data sheet and it's registers, the data sheet says that it will auto detect PCM and DSD. The only register setting for modes is to set 4-channel mode. There doesn't appear to be a way to use the registers to force stereo or 8-channel mode.

It automatically configures for stereo if I input stereo SPDIF on data 1, which is what I am doing right now. I am OK with this so far.

Will the part automatically configure for 2 channel mode if I input I2S on only the first I2S input? I assume I do not need to input the same data on the 4 I2S inputs? I can just leave them alone, pulled down with the resistors?

It appears that I have to set the register for 4 channel mode and input I2S on the first and third data lines for 4CH.

Will the part automatically configure for 8 channel mode if I input I2S on more than the first I2S input? Then set the registers to 4CH if that is what I want?

Does the same go for stereo and multi-channel DSD?

I suppose I could perform some experiments on the demo board to answer these questions, but I am hoping that you have a quick answer.
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Old 15th February 2008, 04:44 PM   #35
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Hi Ross,

I have a "quick" answer, buyt maybe no the one you wanted. Anyways here it is.

SPDIF input:
automatically goes to @ channel mode, you jsut need to parallel the outputs together on the PCB. Also, you must set the regsiter bit to activate SPDIF mode.

SERAIL/DSD mode.
This is the default mode upon power up, the chip will autodetect between these 2. Now for configuring between 2-8 channel part, there is lots of configureations in there I haven't mentions in the datasheet since the 6 bit noise shaper worked out the best. Register 15 that is not talked about can actually set the quantizer to be of 6/7/8or 9 bits. ( Oh man, Im really opening a HUGE can of worms here I might regret). When making the prototypes I thought that 7 bits was going to be the best tradeoff, however, 6 bits works better for THD+N and DNR. But since I know you guys will want to tinler with it, I might as well tell you what the chip is capable of.

One way to add DAC together is everone on this site is aware if is to simply duplicate the input to many dac's and sum them up. What this buy, well I can get 3dB DNR improvemnt everytime to double the amount of DAC (in theory) Basiaclly uncorrelated noise add RSS and signals add normaly. Antother way woud be to actaully use a larger bit quantizer and route the signals from the quantizer to 2 DAC's, but the noise shaper is actaully now has an extra bit in it. This chip does both. You can simple dupilicate the data input input header and then add up the outputs in an analog circuit on the board, or you can program the chip to use a larger quantizer. Doing this, prevents the need to send the same data in all the inputs since now a certain DAC channel is routed into 2 DAC oututs. (man im already regretting this, ohwell, here goes) The DAC is normally a 6 bit quantizer, with the DACx being the summation of the 6 bits, and DAxB being the summation of the inverse of the SAME 6 bits. This is the best all round perfoamnce mode, and this is why the datasheet say reg15 needs to be set to 8'b00000000. Setting this regsiter to 8'b01010101, which by the way was the mode I thought would work best base on my prototype design, and thats why its the default configuarion, the DAC becomes a 7 bit quantizer (thus reducing out of band noise) and I simple divinded up the 7 bit number coming from the qunatizer into 2 6 bit numbers and inverted 1 of them. Then I send off these new 2 6 bit numbers which the differnce is mathematically identical to the origanal 7 bit number from the quantizer and shipped them off to the analog section. This also results in 8 channels at the input being route to 8 channel at the output. Now, lets go further (were only 1/2 down this road) . if you set the reg 15 to be 8'b10101010 then you get a DAC with an 8 bit quantizer, out of band noise decreses more and so on. Now I shut off 1/2 the internal logic since its not requires, only inputs 1,2,5,6 are now needed since now an 8 bit ouput can be spliced into 4-6 bits numbers. (Channel 1 got merged with channel 3, 2 got mergerd with 4, 5 got merged with 7, 6 got mergerd with 8. This is to keep the mergered channels analog secions as close as possible for device mathing in the chip.) This gobbles up 2 analog sections per input now. That is why 1/2 the figital section is shut off. So this can make you a 4 channel DAC while putting data into only the first 4 channels. Ok, lets goes further, how about a 9 bit quantizer, sure why not, Setting reg 15 to 8'b11111111, now I shut of 6 of the channals internally and only the channels 1 and 2 inputs are routed to about analog sections. Well its probably obvious by now why, but here it is again. 1-9 bit number can be broken into 8-6 bit numbers. Now route the 8-6 bit numbers to the analog sections (remeber that each section is DAC and DACB so there are 2 analog sections per DAC or 16 total in the chip, I think someone already pointed this out in one of the threads on this site) so now with each input taking 8 analog secitons, that is 2 channels.

Alright that was fun. One might ask, why have 8 bits to represent swtiching between 4 states, should that only need 2 bits. Sigh..............., yes. Here goes again. If you set reg 15 to 8'b00000010 something else happens. Now its 7 channel DAC.

Reg 15 is mapped like this

r15 [7:6] q_size_68; //2'b00 => Quantizer = 6 bits
//2'b01 => Quantizer = 7 bits
//2'b10 => Quantizer = 8 bits
//2'b11 => Quantizer = 9 bits

r15 [5:4] q_size_24; //2'b00 => Quantizer = 6 bits
//2'b01 => Quantizer = 7 bits
//2'b10 => Quantizer = 8 bits
//2'b11 => Quantizer = 9 bits

r15 [3:2] q_size_57; //2'b00 => Quantizer = 6 bits
//2'b01 => Quantizer = 7 bits
//2'b10 => Quantizer = 8 bits
//2'b11 => Quantizer = 9 bits

r15 [1:0] q_size_13; //2'b00 => Quantizer = 6 bits
//2'b01 => Quantizer = 7 bits
//2'b10 => Quantizer = 8 bits
//2'b11 => Quantizer = 9 bits

where q_size_xx is the "Quantizer size of the coresponce internal DAC.

so setting reg 15 to 8'b00 00 00 10, sets DAC 1 and 3 into 8 bit mode, this means that channel 1 and 3 are megeges, and all others are independent. So data on input for channel 3 will be ignored. If you set the reg 15 to 8'b00 00 10 00, then channels 5 and 7 are merged. and you again have a "7 channel DAC" Notice that the merging. all happens on the same side of the chip. For example, DAC 1 and 3, 5 and 7 are on the right side of the chip. DAC's 2 and 4, 6 and 8 are on the left. This is for the device matching again. Now what if you want to set all the "Left" DAC's (2/4/6/8) to be 1 mother 9 bit noise shaper, and set the other side of the chip to be 4 indepentdace DAC's, thus making a 5 channel DAC. Well set reg15 to 8'b11 11 00 00, for 1 9 bit DAC + 4-6bit DAC's, or even 8'b11 11 01 01 for 1-9bit DAC, and 4-7 bit dacs. I think im going to stop here.

So all that being said, I found that simple using 6 bit mode and running the same data into the inputs and paralleing the outputs, the THD+N and DNR , for the general case, was better, however there are some modes you can tweak and get better perfomance with the other seting, but were taling same difference of 1dB of so.
With that being said, I bet you all now can appreciate why I just chose to say reg 15 set to 8'b00 00 00 00 and be done with it. But I know you guys will tinker with it, so I wanted to let you know, most of our cusmtoners though, really do not want this kind of detail.
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Old 15th February 2008, 05:02 PM   #36
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I would very much like to evaluate the chip. I would be doing my own layout so I just need sample chips, not an eval-board. How can the chips be purchased?

Thanks!
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Old 15th February 2008, 05:17 PM   #37
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OK. Thanks for the answer, Dustin. That will give me something to tinker with over the weekend
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Old 15th February 2008, 10:05 PM   #38
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Com'n, Dustin, you know what we really want to know, not just those info on the surface...

So how the DEM is done? And the "summation" is done?
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Old 15th February 2008, 10:39 PM   #39
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finneybear,

Sounds like you want the schematic, the GDS database, RTL code, and even a picture of the silicon. You know I cant do that, it may be my design, but its not my money put up to build the chip. So I can answer questions about the general nature, but to say exaclty what inside the chip, there is no way ill be allowed to do that at this point.

Sorry about this, but thats the way it is.


Thanks

Dustin
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Old 15th February 2008, 11:02 PM   #40
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No no Dustin, I am not interested in your RTL or behavioral codes.

Cant you talk a bit more about the patterns to do the assignment in DEM or show us a simple diagram about how the outputs are put together? You know, things people can discuss in a conference?
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