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Old 6th March 2008, 04:27 AM   #291
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The PLL in this chip is going to modify the phase noise characteristic, so getting spendy with fancy XOs will yield diminishing returns, at some point.

I'm interested in hearing more about FuriousD's "super DAC" concept. FPGAs are quite affordable these days.
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Old 6th March 2008, 04:40 AM   #292
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Too much trouble for me, FPGAs LOL. Sharc DSP is cheap and easy to work with.

Quote:
Originally posted by rossl
Dude, I'm listening to it right now. It sounds good.
Did you blind test it against a clock such as I mentioned? :P
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Old 6th March 2008, 07:08 AM   #293
BSHAW is offline BSHAW  United States
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Default ESS Sabre DAC Availability

I am Bryan Shaw and as Dustin mentioned previously, I am the distributor for ESS Technology in North America.

I do have availability of both eval boards and silicon. My website is not the best way to contact me as we are working out a few bugs in the submission process.

You can send me an email at bryan@shawelectronics.com or call me at (281)257-2814. I will get back to you ASAP.

Bryan Shaw
Shaw Electronics LLC.
(281)257-2814
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Old 6th March 2008, 07:47 AM   #294
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Quote:
Originally posted by rossl
I'm using a Crystek part on the demo board right now. 49.152M. It's a two dollar part with 0.5pS typ jitter spec. I wonder how much more performance can be purchased for 50X the price?
I agree with abzug. The jitter spec of 0.5ps is utterly meaningless. Can you either post the Crystek part number or quote the phase noise specification. For $2 you'll be getting a pretty cheap cut of crystal with lousy close in phase noise.

Remember that phase noise on the clock close in to the carrier is vital for a high end DAC. I've ordered 3x of the 44.1584 MHz parts today, so 2x are up for grabs elsewhere if wanted. Let me know.
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Old 6th March 2008, 08:05 AM   #295
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Default SuperDAC

Quote:
originally posted by mako1138

The PLL in this chip is going to modify the phase noise characteristic, so getting spendy with fancy XOs will yield diminishing returns, at some point.

I'm interested in hearing more about FuriousD's "super DAC" concept. FPGAs are quite affordable these days.
I have gone over the Texas datsheets again and I cannot find the one that I thought allowed 32-Bit input. The Wolfson does, but the THD is not good. Have Texas changed the PCM1972/ PCM1794?

I am redoing the Matlab work on the filter to see if I can scale things to work on 24-Bits. It wont be that easy as there is no real way to tell in I2S if you have 16 or 24 bits, so we could easily waste 8-bits on zeros! I may have to include some options to select the input bit length externally. Then 16-Bit data becomes very viable for 24-Bit output.

In the absence of a Texas or AD part with 32-Bit input, the general plan is now to work with the ESS part. Ultra low noise clock PSU circuit (John Westlake has posted some good work on this), Crystek CVHD-930 as the clock part with maybe some buffering of the input data to remove the jitter. I need to read up some more on what Dustin is doing in the ESS part.

Dustin can you save me some time here and post the answer here please? Does the Sabre DAC use an internal PLL and buffer to reclock the data? does the DAC at the output clock the data out using this PLL clock or does it use the input master clock?

Filter, an improved version of that specified for the DAC64 probably implemented in DSP. If there are any DSP programmers out there who want a project, i'll provide hardware and Matlab C source and filter coeff's. My DSP implementation skills are a little lacking here.

DAC PSU will be ultra low noise. Maybe something "super-regulator" based. I need to review the options here.

Then simplest output stage possible to filter whilst avoiding the problems of RF foldown and feedback loop corruption. (Abzug if you can't see it you aren;t looking in the right place for it)

I may also include something like the Bridgeco or similar network music interface to give me access to my network music library. I had a play with the new logitech remote the other day. Damned sexy and hopefully goodnight to Sonos!
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Old 6th March 2008, 08:18 AM   #296
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Default Re: SuperDAC

Quote:
Originally posted by FuriousD
[B]
Dustin can you save me some time here and post the answer here please? Does the Sabre DAC use an internal PLL and buffer to reclock the data? does the DAC at the output clock the data out using this PLL clock or does it use the input master clock?
No PLL's, the principal he use is explained in one of his papers.
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Old 6th March 2008, 08:35 AM   #297
rossl is offline rossl  United States
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Quote:
Originally posted by abzug
Too much trouble for me, FPGAs LOL. Sharc DSP is cheap and easy to work with.


Did you blind test it against a clock such as I mentioned? :P

Quote:
Originally posted by FuriousD

I agree with abzug. The jitter spec of 0.5ps is utterly meaningless. Can you either post the Crystek part number or quote the phase noise specification. For $2 you'll be getting a pretty cheap cut of crystal with lousy close in phase noise.

Remember that phase noise on the clock close in to the carrier is vital for a high end DAC. I've ordered 3x of the 44.1584 MHz parts today, so 2x are up for grabs elsewhere if wanted. Let me know.

No, I didn't blind test it against the $100 VCXO. I have had the demo board for a few weeks and don't have any $100 clocks on hand.

You may want to review all the posts in the thread. I have already replaced the 20 cent crystal on the demo board with the two dollar Crystek C3391 part. It was a great improvment. My question is... how much more improvment are you going to get by throwing money at the problem?

There are several technical problems with your suggestion, also. I don't think that the results will be that great from wiring an 80MHZ clock into a board with jumper wires. Without an unbroken ground plane and very short wires between the oscillator and the X-in pin of the DAC part, we aren't going to realize the full potential of the clock. We would also need a clean 3.3V supply delivered to the clock, and that will not be fully realized without a ground plane and good bypassing.

I would have to do a proper PCB layout to do a valid comparison.

Are you guys sugesting that the guys at ESS ship their demo boards with $100 VCXO's ???

The parts cost of the demo board, as it is, is probably less than $100. Your suggestion would more than double the parts cost of the board. At the places I have worked, such a suggestion would earn you a boot in the butt from a bean counter.

Since you have brought it up, I looked around and discovered Digikey has the fixed frequency version ( not a VCXO ) for $28.24

http://search.digikey.com/scripts/Dk...me=744-1055-ND

I ordered some just to test it out.

By the way, go back and look at the jitter spec on the PDF of that $100 oscillator. 12KHz.
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Old 6th March 2008, 08:55 AM   #298
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Quote:
originally posted by rossl

Since you have brought it up, I looked around and discovered Digikey has the fixed frequency version ( not a VCXO ) for $28.24

http://search.digikey.com/scripts/D...ame=744-1055-ND

I ordered some just to test it out.

By the way, go back and look at the jitter spec on the PDF of that $100 oscillator. 12KHz.
Again you are really missing the point. Use the attached website to calculate the jitter based on the phase noise. Then you may understand a bit more of where the figure for the CVHD-930 in picoseconds comes from. I have spent a long time finding good crystals and they are very few and far between. http://www.jittertime.com/resources/pncalc.shtml

As for the other digikey Crystek crystal, you have suggested a crystal with unspecified close in phase noise, which would suggest that the curve rises upwards pretty sharply below the last data point spec'd of 1kHz. (I know this to be the case as I have data on this family from Crystek and have previously looked at them)

Crystals for Audio DAC's / ADC's have different requirements from most telecoms applications. No-one is suggesting that ESS should ship an evaluation board with a $100 crystal fitted. The eval board is supposed to show you functionally how to use the part. You can always improve in each area depending on how much you want to spend. Given the technological superiority of the ESS modulator it would make sense to see how far this can be taken.
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Old 6th March 2008, 09:18 AM   #299
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I spoke too soon; there is a "DPLL" in the block diagram, but upon rereading the white paper that particular block seems to be the magic jitter-reducing unit. Sorry.
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Old 6th March 2008, 10:48 AM   #300
rossl is offline rossl  United States
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Quote:
Originally posted by FuriousD

Again you are really missing the point.
I didn't miss the point. I fully understand the implications of the phase noise in the clock of an ASRC.

You seem to miss the point. There is no need for a $100 VCXO with this Sabre8 part.

You also seem to miss the point that very few people in this world will be willing to pay the cost for one in a consumer product.
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