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Old 26th July 2014, 09:26 PM   #2361
miero is offline miero  Czech Republic
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pkr708: check these undocumented registers Sabre DAC Datasheet: The Missing Parts | H i F i D U I N O
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Old 27th July 2014, 10:16 AM   #2362
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Quote:
Originally Posted by pkr708 View Post
If the noise-bumping is somehow connected to the limit cycles, then it may not appear (or appear less) with real - non-sine - music signal, am I right?
Yes, less, but if the music signal happens to wander just around the critical level then it can modulate the noise floor.

(many R2R's tend to get bumpy THD+N vs level plots too, when signal crosses the boundary where next 2x element jumps in, but there it's mostly THD because the error cannot be whitened)

Quote:
Still, I don't get why the noise falls down again when amplitude is rising from 35dB up. There should be even less space for element scrambling...
Does it really fall down, or the SNR just improves because the signal itself comes stronger? The THD+N vs level plots look like the noise stays pretty much at the new level, as expected. Although maybe improving a little possibly due to some modulator dither kicking in and reducing the error.
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Old 27th July 2014, 05:17 PM   #2363
pkr708 is offline pkr708  Czech Republic
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Quote:
Originally Posted by miero View Post
pkr708: check these undocumented registers Sabre DAC Datasheet: The Missing Parts | H i F i D U I N O
Thanks!


Quote:
Originally Posted by Signalyst View Post
Does it really fall down, or the SNR just improves because the signal itself comes stronger? The THD+N vs level plots look like the noise stays pretty much at the new level, as expected. Although maybe improving a little possibly due to some modulator dither kicking in and reducing the error.
Yes, see table in .xlsx attached to post #2351 - measurement of best and worst channel of my DAC module.

The integrated THD+N error signal amplitude, which is about ~1.4uV for very low level signals, suddenly jumps to 8.35uV on -35dBFS, but again falls to ~3.3uV near full scale (where majority of it is probably formed by THD itself, not noise).
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Old 28th July 2014, 04:56 PM   #2364
bbp is offline bbp  China
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Quote:
Originally Posted by pkr708 View Post
Hi Paul,

I was dealing with the same problem, thinking that it is my design's issue, until I've been told about your post.

I've reached over -124dB THD and ~1.6uVrms audio band noise, which yields about 121dB DNR (my module is 8 channel with 1.6V output voltage). But interestingly, I found out that every channel has different full-scale THD+N, varying from -113 to -116.5dB. I spent tens of hours trying to solve it!

After reading your post, I sat again to R&S UPV and measured THD+N vs. amplitude and got the same result as you. There really is a bug manifesting itself between -35 and -36dBFS by steep noise rise, while THD level is not affected. However, I think it is a output, not input stage bug, because it acts differently on each channel.

Channels 2 and 6 are performing best, while 1, 7 and 8 are the worst. All measurements has been made with I2S input in asynchronous mode and the bug is present with both cheap Fox and high-quality PLEtronics MCLK oscillator.

Unfortunatelly, I can't (or at least don't know how to) make a plot of noise vs. DC level (in dBFS). Could you try to do it on your AP? I think there may be only single (or few) problematic DC level/s corresponding to certain input data levels, which could be filtered out by DSP to solve this problem.

I've sent a message to ESS tech support more than week ago... still no reply.

BR,
Pavel

Click the image to open in full size.

Thanks for your input.
To my system, the issue did not appear sometimes when I power my DAC up.
In that case, the noise for whole range is ultra clean. as you can see from my measurement.

But, I am afraid that ESS will not reply a single word to this issue. Because many customers are using ES9018 in their products. Like WEISS, etc.

I think it will not affect listening most of the time, but I insist on my standard. This bug can not meet my requirement unless I can find a stable way to avoid this.

Thank you.

BR
Paul Lu
__________________
calm down and enjoy your time in experiment
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Old 29th July 2014, 12:13 AM   #2365
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by Shinja View Post
Hi paul

How does your "default operation" occur, depend on some register setting or randomly?
How do you feed the master clock to ES9018, local 40-100MHz oscillator or sync with your source equipment?

A japanese garage audio maker "AIT lab" showed some non-harmonic spurious occurs when synchronizing clock with source, due to its jitter reduction system.
DAC
upper image: without his secret timing trimming(?)
middle image:same, but 6kHz signal, that is the freq divided sampling rate with integer.(192k/32=6k)
bottom image:with his trimming
In the blog post by Mr. Kakuta of AIT Lab in Japan, as "shinja" explained above, he reported that the emergence of spurious he observed was not a stable event.
At each power-on, the spurious appeared or not appeared.
He imagined a possible variation in timing of internal initialization of DPLL after each power-on might caused the problem.

Paul's post reminded me of the report by Mr. Kakuta.

Last edited by Bunpei; 29th July 2014 at 12:22 AM.
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Old 29th July 2014, 02:50 PM   #2366
Shinja is offline Shinja  Japan
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oh I fogot to mention it in that post.
thank you bunpei
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Old 19th August 2014, 12:55 AM   #2367
Bunpei is offline Bunpei  Japan
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My main system uses ES9018S chips in a synchronous master clocking scheme with 45/49 MHz low phase noise oscillators.
Only for such conditions as MCLK freq=256 x fs, DPLL Nobandwidth setting brings an output sound with periodic unlock events of which interval is constant. As for 45 MHz master clock, the interval is appoximately 24 seconds.

In spite of the scratch noise-like interrupt, the sound quality with DPLL Nobandwidth is superior and I love it. It is the best sound the DAC chip provides.

Does anyone here experience the DPLL Nobandwidth sound as well?
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Old 21st August 2014, 11:43 AM   #2368
Shinja is offline Shinja  Japan
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I found wolfson suggest DC sweep test to check how DEM work as expected.
http://www.wolfsonmicro.com/media/77...Whitepaper.pdf
see page 4(85)
It is interesting that DEM have similar characteristics to noise shaping ,their noise frequency responce(?) and idle pattern problem.
I have not known latter.
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Old 26th August 2014, 12:01 AM   #2369
cu6apum is offline cu6apum  Russian Federation
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Quote:
Originally Posted by Bunpei View Post

First, I'd like to have a clear understanding on the meaning of "True" and "Pseudo" in the differential mode and to appreciate your comments.

My basic understanding is;
1. In "True" differential mode, an normal output signal "+" appears between A_GND pin and "DACn" pin and counterpart output signal "-" appears between A_GND pin and "DACnB" pin.
2. In "Pseudo" differential mode, a single output signal appears between "DACn" pin and "DACnB" pin.

What I can't understand well is how this difference would affect the design of I/V stages, especially in terms of GND handling. In my case, as I only use transformer I/V stage or earphones and use no GND pins, no difference is recognized.
I second this question and, in addition, would love to know, is it so, or not. There's virtually no info on what this "true/pseudo" means and how it correlates with quantizer depths. In early posts Russ said that "true" is not available beyond 6 bits; the experiments did show it is.

Could you please descramble me on this matter? Many thanks!!!
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Old 17th September 2014, 09:57 PM   #2370
Coris is offline Coris  Norway
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Hi Bunpei

As I know from your previous posts, you may have a quite extended experience with the digital files structure.
I have a very precise question: there is (may be) a characteristic structure for how the silence/pause is represented in a digital file, versus the rest of the contiguous (compact) analogue coded (originally analogue to digital converted) digital file?
I mean it have to be a difference in how is represented the information in a continuous flow of bits coded at the recording, and the added silence just after the last bit of information of that file (for pause reasons, or so). There is not here about the silent passages of a recording (inside a digital file), but the so called silence, when there is no more information to be streamed into the (DAC) system. It seems to me that it may be streamed a kind of information anyway, until the mute is activated, or another conversion of a next digital file it starts.

What I ask this question?
I have noticed recently, while experimenting with ES9018, that it behave different (resulted outputted sound), just after the last bit of information is decoded (converted), and when this supposedly added silence starts. After this variable in time "silence" (pause between files), it may be started the streaming of another file (previously it was read it its header), or it is turned on the Mute mechanism (the playback is stopped).
Here it is happen something, which lead me to the conclusion that it have to be a different digital structure, in how these events are digitally represented. I only need a confirmation (or not) at this hypothesis ...

I do hope I succeeded to make me understood with this text here (maybe a little bit out of topic)...

Thanks for your or another one`s eventual replay.

Last edited by Coris; 17th September 2014 at 10:01 PM.
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