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Old 16th May 2013, 08:09 AM   #2231
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Quote:
Originally Posted by dusfor99 View Post
Hi Calvin,

Im not 100% sure what type of information you are after, but I can assure you the numbers posted on the ESS sites are true. The third party measurement was done by Steve Peterson of ATECS. I think you will find he would be a reliable source.

ATECS - Audio Test Engineering Consulting Services


Since the numbers were posted in the datasheets, we have actually made better measurements, but have chosen not to bother updateing the datasheets for confusion. The AD797 has consistantly provided the best numbers getting -135dB of DNR (A-weighting) and can do -120dB of THD+N unweighted across from 20 to 20k. We have shown other OPAMPs can do >118 THD+N at 1kHz, which is impressive, but, try measure at 5k and 7k. Thats were almost every other device tested showed "issues" dropping into the -110dB THD+N or lower. The DAC is sensitive to the power supply, but this is acutally on purpose, It would have been very tough to generate a analog reference that can achieve -135dB A-weighted 20-20k on the chip that has 1024 DAC's (64 per pin, 16 pins).

As for the sound of the DAC, it is greatly influenced by the parts connected to it. I believe this is where audio companies can come in and use their knowledge and expertise to have some product differentiation.

For the output stage:

I dont think we ever claimed a current source, but rather a "current mode". The current mode is simply when the current going in and out the pin of the chip is sensed. This mode has the benefit of cancelling 2nd and 3rd harmonics of some of the internal ananlog circuitry. The "voltage mode" is when the pin of the chip has a voltage on it that is being sensed. While this has the 2nd and 3rd hormics (at the -100dB level or so), some people have even claimed this mode is more "tube-like" Its all personal prefference.

I hope this helps out a little.

Thanks

Dustin
Bunpei, to save you for the searching I quoted the post (1532).

It is soon three years ago since I added this info to my equations..

There are 1024 1 bit DACs inside that have a logically default configuration of 64 per (DAC output) pin, but can be re-configured as you like - so it is possible to partition and route and manipulate data nearly as you wish.. Go figure..

My IR remote control system have implemented the possibility to configure over 16 million combinations (register settings) and have been the ultimate tool to explore the chip..

My current DAC revision utilizes all 1024 levels for one audio channel - so two channels are 1024 levels pr. channel as I use on DAC chip pr. channel..

Last edited by RayCtech; 16th May 2013 at 08:12 AM.
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Old 16th May 2013, 09:20 AM   #2232
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Quote:
Originally Posted by RayCtech View Post
There are 1024 1 bit DACs inside that have a logically default configuration of 64 per (DAC output) pin, but can be re-configured as you like - so it is possible to partition and route and manipulate data nearly as you wish.. Go figure..

My current DAC revision utilizes all 1024 levels for one audio channel - so two channels are 1024 levels pr. channel as I use on DAC chip pr. channel..
To me It sounds more like 10-bit single ended or 10-bit pseudo differential
- I have no idea It could be possible or not - rather than 9-bit true differential.
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Old 16th May 2013, 11:23 AM   #2233
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Originally Posted by wktk_smile View Post
To me It sounds more like 10-bit single ended or 10-bit pseudo differential
- I have no idea It could be possible or not - rather than 9-bit true differential.
I am finished with the ES9018 experiments now, but if not I would have tried to build a 4 chip system running in discrete 10 bit true differential mode.

With the 9 bit true differential version I have the reference I needed to benchmark the discrete DAC I have in works.

One bit resolution is lost to remove the #noise...
With the #noise in action it sounds like a bad AM radio in OSF bypass mode...

Last edited by RayCtech; 16th May 2013 at 11:31 AM.
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Old 16th May 2013, 03:12 PM   #2234
Bunpei is offline Bunpei  Japan
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Hi, Raymond,

Thank you very much for showing me Dustin's post in the past.
However, ...

Quote:
Originally Posted by RayCtech View Post
... There are 1024 1 bit DACs inside that have a logically default configuration of 64 per (DAC output) pin, but can be re-configured as you like - so it is possible to partition and route and manipulate data nearly as you wish.. Go figure..
If you read what Dustin has written previously in this thread you will find that there are not any "arbitrary configurations" of 1 bit DACs at all ...

Those 64 x 1 bit DAC are apparently bound to one output pin. You can't assign one of them to another pin. So, we must handle them as a group of 64 pieces.

Quote:
Originally Posted by RayCtech View Post
... With the 9 bit true differential version I have the reference I needed to benchmark the discrete DAC I have in works. ...
Wktk_smile reported that no 9 bit true differential mode gave normal sounds while you say 9 bit true differential is established. I was much confused with this. I'm afraid that both of you are based on different definitions of "true-differential".

Last edited by Bunpei; 16th May 2013 at 03:26 PM.
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Old 16th May 2013, 05:52 PM   #2235
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Originally Posted by Bunpei View Post
I'm afraid that both of you are based on different definitions of "true-differential".
True differential are true differential so it is not definition but implementation that are different
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Old 17th May 2013, 11:08 PM   #2236
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by Bunpei View Post
 A six bit DAC should have 64 levels including 0.
6 bit: values ... 63 - 0

A nine bit DAC should have 512 levels including 0.
9 bit: values ... 511 - 0
In the case we need to yield 9 bit levels by a combination of eight 6 bit values:
Target value 511
DAC1 - 63
DAC2 - 63
DAC3 - 63
DAC4 - 63
DAC5 - 63
DAC6 - 63
DAC7 - 63
DAC8 - 63
------------------------
Total 504

Alas, the sum of 8 individual DAC output is less than the ideal target value 511! How can we compensate the shortage? 
Raymond's indication and explanation on Dustin's post has led me to more reasonable understanding. Thank you very much, Raymond.

I found the quantizer bit length notation is somewhat different from the conventional notation used for multi-bit DACs.

6 bit quantizer => 64 x 1 bit DACs : it can represent 65 levels including 0.
6 bit quantizer: value range [64 - 0]

9 bit quantizer => 512 x 1 bit DACs: it can represent 513 levels including 0.
9 bit quantizer: value range [512 - 0]

In the case we can yield 9 bit integer output values by a combination of eight 6 bit integer values:
Target value 512
DAC1 - 64
DAC2 - 64
DAC3 - 64
DAC4 - 64
DAC5 - 64
DAC6 - 64
DAC7 - 64
DAC8 - 64
------------------------
Total 512

Target value 0
DAC1 - 0
DAC2 - 0
DAC3 - 0
DAC4 - 0
DAC5 - 0
DAC6 - 0
DAC7 - 0
DAC8 - 0
------------------------
Total 0

Now, we have sufficient values!
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Old 22nd May 2013, 10:08 AM   #2237
Shinja is offline Shinja  Japan
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Why do the Avcc buffer in ES9008's evaluation board not oscillate,
even with AD797 which is known as easily oscillate opamp and 2uF enormous capacitive load?
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Old 22nd May 2013, 02:40 PM   #2238
roender is offline roender  Romania
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Quote:
Originally Posted by Shinja View Post
Why do the Avcc buffer in ES9008's evaluation board not oscillate,
even with AD797 which is known as easily oscillate opamp and 2uF enormous capacitive load?
Try with 100nF
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Old 23rd May 2013, 07:36 AM   #2239
qusp is offline qusp  Australia
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Quote:
Originally Posted by Shinja View Post
Why do the Avcc buffer in ES9008's evaluation board not oscillate,
even with AD797 which is known as easily oscillate opamp and 2uF enormous capacitive load?
a small capacitor of some 50-100pf in series with another resistor, together bypassing the FB resistor, increases capacitive drive ability for the AD797, plus here we are talking about low voltage and its not driving a low impedance. needs careful layout, especially at unity gain, but it works no problem.

alternatively, try lme49990
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Old 23rd May 2013, 12:51 PM   #2240
Shinja is offline Shinja  Japan
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thank you roender , qusp.

I read AD797's datasheet and found a description about paralleling small C <33p with 100ohm resister.
Although there is no such C or any effective snubber but a simple voltage follower...

Quote:
plus here we are talking about low voltage and its not driving a low impedance.
Could you explain in detail?
The AVcc buffer drives half of the current output from ES9008's analog output in the evaluation board's configuration.
The AC analog output is differential ,thus its load is always almost DC 2.112mA*8DACs= 16.896mA(=195 ohm!) and 1+1uF and offset generator.
I feel it is not so light load though it have (ideally) no voltage swing ,but does it have any influecnce for stability?
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Last edited by Shinja; 23rd May 2013 at 01:16 PM.
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