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Old 13th April 2013, 11:35 AM   #2221
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I tried no_bandwidth setting too, with Buffalo II and Ianís FIFO+si570 reclock board and SDtrans.
Ianís si570 board allows me changing mclk frequency easily and that was very helpful.

44,1k wav with 11.2896Mhz MCLK = 95sec steady lock period, then dropped lock and relock quickly
88.2k wav with 22.5792Mhz MCLK = roughly 48sec.
96k wav with 24.576Mhz MCLK = roughly 45sec.

Same result with the others.

When playing 44.1k wav with higher MCLK frequencies, No bandwidth is completely useless,

but I repeated trying relock manually with patience, sometimes suddenly succeeded to lock in very short period. In this case, DAC loose lock after several seconds and seems never re-lock again automatically
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Old 13th April 2013, 12:15 PM   #2222
Bunpei is offline Bunpei  Japan
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Hi, wktk_smile,

Thank you very much for your report!

Do you perceive a better spacial focusing within the 95 seconds?

Bunpei
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Old 13th April 2013, 12:44 PM   #2223
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Quote:
Originally Posted by Bunpei View Post
Hi, wktk_smile,

Thank you very much for your report!

Do you perceive a better spacial focusing within the 95 seconds?

Bunpei
The improvement in SQ is not so audible for me.

Sometimes I feel slightly better focus, sometimes I feel it's leaner.
And It seems the audibility of these characteristics is varied with genre of music or quality of recordings.
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Old 13th April 2013, 03:05 PM   #2224
Bunpei is offline Bunpei  Japan
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Thank you very much for your frank impression!
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Old 16th April 2013, 11:45 PM   #2225
Bunpei is offline Bunpei  Japan
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It's just a kind of funny experiment.

Tackbon in Japan tried a synchronous master clocking of 1.4112 MHz on 44.1 kHz/16 bit PCM source under OSF=OFF condition. The master clock was prepared by dividing a BCLK.
He happened to get a lock only on DPLL Bandwidth, Best default or High. He describes the obtained sound quality, "like an AM radio sound".
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Old 25th April 2013, 12:47 PM   #2226
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Default imitating true 9-bit differential mode

test was done by sdtrans - Ian's FIFO + si570board - BuffaloII(ES9018) + Arduino(Hifiduino code, modded a bit)

First of all, As far as I know, true differential mode + 9-bit quantizer register
settings only result in distorted sound.

Output pins are rearranged as shown in attached drawing(and of course each dac polarity must be re-programed)
register settings are :
- mono mode
- Pseudo differential mode
- 9-bit quantizer


results:

Positive output + DC block cap connected to SE input of the amplifier
- Clean audio playback, not distorted like true-differential register setting under 9bit quantizer mode.

Positive and Negative output followed by line transformer (for BAL-SE conversion)
- Clean audio playback.

Positive and Inverted Negative output (now same polarity with positive output), followed by line transformer
- Successfully cancelled.


Sonice difference, 9-bit vs 8-bit true differential (only register settings were changed)

Under 9-bit quantizer mode, the sound is less bold, and attacks are more solid, noises contained in recordings are more audible. Although those difference are very small amount and It required me repetitive comparison over
and over.
Attached Images
File Type: jpg wiring.jpg (21.4 KB, 548 views)
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Old 25th April 2013, 04:23 PM   #2227
glt is offline glt  United States
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Hi wktk_smile,

Thanks for the sound impression between 9 bit and 8 bit.

I didn't quite understand how you "imitated" 9-bit true differential.
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Old 26th April 2013, 09:13 AM   #2228
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to glt

From Dustin's post#35 in this thread.

the DAC becomes a 7 bit quantizer (thus reducing out of band noise) and I simple divinded up the 7 bit number coming from the qunatizer into 2 6 bit numbers and inverted 1 of them. Then I send off these new 2 6 bit numbers which the differnce is mathematically identical to the origanal 7 bit number from the quantizer and shipped them off to the analog section.

I think he meant 7-bit pseudo differential mode there.


9bit number can be split to two 8bit ones, only under pseudo differential register setting. Let's call them as half-9bitA and half-9bitB.

Usually one of them are just inverted (and assigned to DACXB), thus we can get complete audio output only after Bal-Se conversion.

If same polar these half-9bitA and half-9bitB connected in paralell is identical to complete 9-bit quantizer mode output, we can get two 9-bit SE output
from one IC without BAL-SE conversion circuit.

Then Additional polarity programming and Mono mode setting should enable us to "imitate" true differential mode.
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Old 15th May 2013, 12:52 PM   #2229
Bunpei is offline Bunpei  Japan
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I'd like to discuss some details of quantizer bit length expansion option on ES9018.

The basic hardware design of one Analog DAC section of ES9018 is of 6 bit.
A "qunantizer bit length expansion" technique is a combination of multiple 6 bit DAC sections to obtain higher resolutions equivalent to those of 7, 8 or 9 bit DAC.

Let's think of a definite case.
A six bit DAC should have 64 levels including 0.
6 bit: values ... 63 - 0

A nine bit DAC should have 512 levels including 0.
9 bit: values ... 511 - 0
In the case we need to yield 9 bit levels by a combination of eight 6 bit values:
Target value 511
DAC1 - 63
DAC2 - 63
DAC3 - 63
DAC4 - 63
DAC5 - 63
DAC6 - 63
DAC7 - 63
DAC8 - 63
------------------------
Total 504

Alas, the sum of 8 individual DAC output is less than the ideal target value 511! How can we compensate the shortage?

Hi, Raymond, do you have any idea?
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Old 15th May 2013, 02:44 PM   #2230
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Quote:
Originally Posted by Bunpei View Post
I'd like to discuss some details of quantizer bit length expansion option on ES9018.

The basic hardware design of one Analog DAC section of ES9018 is of 6 bit.
A "qunantizer bit length expansion" technique is a combination of multiple 6 bit DAC sections to obtain higher resolutions equivalent to those of 7, 8 or 9 bit DAC.

Let's think of a definite case.
A six bit DAC should have 64 levels including 0.
6 bit: values ... 63 - 0

A nine bit DAC should have 512 levels including 0.
9 bit: values ... 511 - 0
In the case we need to yield 9 bit levels by a combination of eight 6 bit values:
Target value 511
DAC1 - 63
DAC2 - 63
DAC3 - 63
DAC4 - 63
DAC5 - 63
DAC6 - 63
DAC7 - 63
DAC8 - 63
------------------------
Total 504

Alas, the sum of 8 individual DAC output is less than the ideal target value 511! How can we compensate the shortage?

Hi, Raymond, do you have any idea?
0 is a value so you get the 512.
In 9 bit true mode it is actually 1024 levels as each phase have 512...
If you read what Dustin have written previously in this thread you will find that there are not any 6 bit DAC engines at all...
It is only a default of 6 bit data that are sent to the DAC section...

Last edited by RayCtech; 15th May 2013 at 02:49 PM.
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