ESS Sabre Reference DAC (8-channel) - Page 221 - diyAudio
Go Back   Home > Forums > Source & Line > Digital Line Level

Digital Line Level DACs, Digital Crossovers, Equalizers, etc.

Please consider donating to help us continue to serve you.

Ads on/off / Custom Title / More PMs / More album space / Advanced printing & mass image saving
Reply
 
Thread Tools Search this Thread
Old 8th April 2013, 01:09 AM   #2201
Bunpei is offline Bunpei  Japan
diyAudio Member
 
Join Date: Aug 2008
Quote:
Originally Posted by AAK View Post
... On my setup with DPLL Bandwidth set to "No Bandwidth" using spdif inputs the ES9018 completely losses lock, but regains a very steady lock when the DPLL BW is multiplied by 128. ...
I hope you understand my point. Those Japanese people are challenging to "No bandwidth" DPLL setting which is very difficult to achieve.

Quote:
Originally Posted by Shinja View Post
it is whird. Why does tackbon not generate BCLK via dividing MCLK?
Can it call "sync MCLK"?
I think you can ask it to him directly by posting your comment on Tackbon's blog page.

Quote:
Originally Posted by roender View Post
You are right, BIII doesn't support DPLL "No Bandwidth" setting.
What confuse me is why DPLL is up and running in sync mode?
To be exactly, there is no "sync mode" on ES9018 architecture. DPLL is always ON. However, it is actually "free wheeling" ( this is Russ'es nice wording ) when a synchronous master clock is injected.
  Reply With Quote
Old 8th April 2013, 01:30 PM   #2202
AAK is offline AAK  United States
diyAudio Member
 
Join Date: Jul 2004
Location: Florida
Hi Bunpei,

I understand your point. I just wanted to point out that with an Spdif Input, 100Mhz asynchronous clock, and the DPLL BW set to "No Bandwidth", my DAC locks when the DPLL Multiplier is set to x128. No lock at all when set x1. Thought maybe this information can help your Japanese friends.

Any ideas why if there's "No Bandwidth" the ES9018 locks when the DPLL Multiplier is set to x128? I have some ideas, but not entirely sure. Thanks!

Best regards,

Al
__________________
Love when you can, Cry when you have to, be who you must, that's part of the plan.

Last edited by AAK; 8th April 2013 at 01:54 PM.
  Reply With Quote
Old 8th April 2013, 04:52 PM   #2203
Bunpei is offline Bunpei  Japan
diyAudio Member
 
Join Date: Aug 2008
Hi, Al,

I have realized that I need to explain our background enough for you.

You mentioned S/PDIF and DPLL multiplier x 128. In this case, the DPLL bandwidth condition is 64 (S/PDIF) x 128 times looser or more relaxed than that of 1(I2S) x 0 (No bandwidth).

The Japanese people do not want the easy locking. They are deliberately challenging the most difficult condition because they once perceived that the resultant sound had the best spacial focusing.

Bunpei
  Reply With Quote
Old 8th April 2013, 05:05 PM   #2204
Bunpei is offline Bunpei  Japan
diyAudio Member
 
Join Date: Aug 2008
We discussed a possible interpretation of the magic period 95 or 96 seconds.

Under the condition;
fs=44.1 kHz, MCLK=11.2896 MHz, BCLK=2.8224 MHz, I2S, OSF=ON
DPLL counter value is 0x3FFFFFFF ( a quarter of 0xFFFFFFFF).
The counter counts BCLK.

0x3FFFFFFF / 44100 / 64 / 4 = approximately 95
( Oversampling ratio is 4 ? )

The DPLL counter might be reset when the counted value reaches to 0x3FFFFFFF and the resetting action may cause the unlock event.
  Reply With Quote
Old 8th April 2013, 06:25 PM   #2205
Account disabled at member's request
 
Join Date: Sep 2007
Location: Multiple...
Quote:
Originally Posted by Bunpei View Post
We discussed a possible interpretation of the magic period 95 or 96 seconds.

Under the condition;
fs=44.1 kHz, MCLK=11.2896 MHz, BCLK=2.8224 MHz, I2S, OSF=ON
DPLL counter value is 0x3FFFFFFF ( a quarter of 0xFFFFFFFF).
The counter counts BCLK.

0x3FFFFFFF / 44100 / 64 / 4 = approximately 95
( Oversampling ratio is 4 ? )

The DPLL counter might be reset when the counted value reaches to 0x3FFFFFFF and the resetting action may cause the unlock event.
Strange interpretation...

The "DPLL counter" will always have a 32bit number that you can read regardless if the data are PCM from I2S input, PCM from SPDIF input or DSD.

If you read the "DPLL counter" repeatedly to a display you will see that the "DPLL counter" number will be relatively stable..

Thus you can calculate the sample rate, the bit frequency etc. and you can then monitor the clocking accuracy or the incoming clocking accuracy - all depending on how you program and how reliable your master clock is. If you know the incoming sample rate you can calculate the master clock frequency. So there are no magic periods related to the "DPLL counter" that causes what you call a "resetting action".

It does not matter if OSF =ON or =OFF => the difference in the result are exactly 64...
So my programming checks if OSF = ON or OFF and then divides by 64 or not to get the correct results..
  Reply With Quote
Old 9th April 2013, 12:11 PM   #2206
CeeVee is offline CeeVee  Portugal
diyAudio Member
 
CeeVee's Avatar
 
Join Date: Dec 2006
Hi Mihai,

What's that IV you are using on post #2188 ?...looks to be quite different from your other one.

You know that's my focus right now ..

My setup is singing but I'm using temporarily a Legato 3.1 as IV...just for starters.

Great work.

Last edited by CeeVee; 9th April 2013 at 12:15 PM.
  Reply With Quote
Old 9th April 2013, 02:35 PM   #2207
roender is offline roender  Romania
diyAudio Member
 
roender's Avatar
 
Join Date: Sep 2006
Quote:
Originally Posted by CeeVee View Post
Hi Mihai,

What's that IV you are using on post #2188 ?...looks to be quite different from your other one.

You know that's my focus right now ..

My setup is singing but I'm using temporarily a Legato 3.1 as IV...just for starters.

Great work.
It isn't an I/V stage, just a buffer and low-pass filter for Sabre DAC in voltage output mode.
  Reply With Quote
Old 9th April 2013, 03:00 PM   #2208
CeeVee is offline CeeVee  Portugal
diyAudio Member
 
CeeVee's Avatar
 
Join Date: Dec 2006
"It isn't an I/V stage, just a buffer and low-pass filter for Sabre DAC in voltage output mode."

...It's always in voltage mode ...


Ok, I'm finishing a PCB design for your IV...Ill post it in the proper thread when i find the right output cap for it, It fits the plug-in PCB...or can be omitted from PCB and connected directly to balanced outputs.

I've got nice music now from my SDTRANS so i can design more relaxed now.
Next step is to get rid of UFL connectors in I2S interface to BIII ( source of my debugging headaches ) and sync master clock to BIII as well using one of IAN's adapters.

Last edited by CeeVee; 9th April 2013 at 03:05 PM.
  Reply With Quote
Old 9th April 2013, 04:04 PM   #2209
Bunpei is offline Bunpei  Japan
diyAudio Member
 
Join Date: Aug 2008
Quote:
Originally Posted by RayCtech View Post
Strange interpretation...
The strangeness is very natural as they are doing something extreme.

Your explanation is completely correct and might be very useful for those who are not familiar with ES9018 architecture as far as you look at its display-level functionality.

However, let's think about the internal mechanism behind the display-level.
In the DPLL_NUM register sets, they latch a normalized 32 bit integer value based on counting of BCLK pulses for a certain period. Behind the register sets, there must be a live counter that is always counting up and to be reset to zero periodically.
  Reply With Quote
Old 9th April 2013, 04:39 PM   #2210
Account disabled at member's request
 
Join Date: Sep 2007
Location: Multiple...
Quote:
Originally Posted by Bunpei View Post
The strangeness is very natural as they are doing something extreme.

Your explanation is completely correct and might be very useful for those who are not familiar with ES9018 architecture as far as you look at its display-level functionality.

However, let's think about the internal mechanism behind the display-level.
In the DPLL_NUM register sets, they latch a normalized 32 bit integer value based on counting of BCLK pulses for a certain period. Behind the register sets, there must be a live counter that is always counting up and to be reset to zero periodically.
You better explain what this "extreme" is

My setup uses synchronous clocking and I can run with master clock = bit clock and up to 90/98MHz clocks - with jitter reduction turned off completely etc.. The DPLL_NUM register do not in any case act as a counter (it is not counting bit clocks from zero to a max value and then resets and starts again like your explanation) - it contains a value that are constant (may vary a little bit up and a little bit down depending on the source used) with the master clock, bit clock, word clock and the filters etc. that are active when playing.
Thus by checking what input (PCM, DSD or SPDIF (by reading registers)) and what filters (by reading registers) that are enabled it is just to divide the DPLL_NUM register value accordingly and get the result you want.

If synchronous clocking are used these calculations can be complicated due to it then can be several alternative clock frequencies in use. Both several different master clock and bit clock and word clock frequencies.

However it is possible to manually override (by register programming) the DPLL_LOCK and force the Jitter eliminator to re-lock to the signal.
From what little you have explained of the "extreme" use I would expect that there are an error in the programming code and the re-locks that happens every 95-96 seconds are caused by this.
Or it may be that your friends can avoid this by simply shut down the Jitter Eliminator that are not needed with synchronous clocking and high quality clocks and when synchronous re-clocking are performed on data, bit and word clocks..

Last edited by RayCtech; 9th April 2013 at 04:53 PM.
  Reply With Quote

Reply


Hide this!Advertise here!
Thread Tools Search this Thread
Search this Thread:

Advanced Search

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are Off
Pingbacks are Off
Refbacks are Off



New To Site? Need Help?

All times are GMT. The time now is 01:04 AM.


vBulletin Optimisation provided by vB Optimise (Pro) - vBulletin Mods & Addons Copyright © 2014 DragonByte Technologies Ltd.
Copyright 1999-2014 diyAudio

Content Relevant URLs by vBSEO 3.3.2