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Old 10th March 2013, 09:38 AM   #2181
roender is offline roender  Romania
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Level sifters are digital circuits that translates 1.2V logic in 3.3V logic. This has nothing to do with the analog stage of the Sabre chip.
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Old 15th March 2013, 11:59 AM   #2182
acko is offline acko  Australia
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Quote:
Originally Posted by Bunpei View Post
I'm sorry that I have not checked whether it is a FAQ or somewhere it is explained.

There are 7 power pins on ES9018 for +1.2V power;
1 VDD_L Analog Power(+1.2V) for Left channels
16 VDD_L Analog Power(+1.2V) for Left channels
20 VDD Digital Power(+1.2V) for core of chip
29 VDD Digital Power(+1.2V) for core of chip
33 VDD_R Analog Power(+1.2V) for Right channels
48 VDD_R Analog Power(+1.2V) for Right channels
61 VDD Digital Power(+1.2V) for core of chip

I understand that "Analog Power" means "related to analog DAC section" of the chip and "Digital Power" means "related to digital processing core section" and all power lines are connect to internal digital circuits.

Does any one have any clear empirical result that it's better for us to assign separate +1.2V regulators for "Analog Power" and "Digital Power" respectively?

I found acko's DAC board provides separate power input terminals.
Both Power and signals are not combined on the AKD12 board to give flexible options, especially if we not sure how the Analog/Digital sections are connected internally. If you feel there is not much to be gained from separating the supplies then simply share them accordingly. But if you look at the 9016 chip this has no AVDD (1.2V) pins, possibly generated internally or connected to chip core DVDD supply and the performance is lower. Maybe there are other factors contributing to this but I have chosen the 'safe' option.
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Last edited by acko; 15th March 2013 at 12:03 PM.
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Old 1st April 2013, 11:42 PM   #2183
Bunpei is offline Bunpei  Japan
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Oh, no commentary replies from ready critic.

To roender & Acko,

Thank you very much for your replies.
To my regret, I can't understand why a level shifter requires an independent +1.2V.
I have no board to try separated power supplies at my hand. I wish I could try.

Bunpei
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Old 2nd April 2013, 12:12 AM   #2184
Bunpei is offline Bunpei  Japan
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Two SDTrans users, "sky" and "tackbone" in Japan are making their efforts on establishing a stable lock with "No bandwidth" setting of DPLL bandwidth parameter under OSF=ON for 44.1 kHz/ 16 bit PCM sources.
They use a carefully prepared 11.2896 MHz synchronous master clock. Sky's assumption is "No bandwidth might be achieved easily particularly when MCLK is 4 x BCLK".

As of now, the longest period they have without any unlock event is about 90 seconds. However, they say the resultant sound in the locked state has the best focusing that they have never experienced. That is the reason why they make their efforts.
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Old 2nd April 2013, 11:19 AM   #2185
roender is offline roender  Romania
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Quote:
Originally Posted by Bunpei View Post
To my regret, I can't understand why a level shifter requires an independent +1.2V.
The level shifters didn't required an independent voltage source, other than the power supply for the core.
My assumption is that it was much simpler to access the shifter supply on the chip by external connection rather than internal.
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Old 7th April 2013, 05:12 AM   #2186
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by roender View Post
... My assumption is that it was much simpler to access the shifter supply on the chip by external connection rather than internal. ...
It could be an assumption.
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Old 7th April 2013, 05:21 AM   #2187
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by Bunpei View Post
... As of now, the longest period they have without any unlock event is about 90 seconds. ...
Totally three people in Japan tried the "No Bandwidth" experiments and all of them got the same longest periods, 96 seconds in spite that they applied such different I2S sources, SDTrans and QA-550.

Does anyone give a possible interpretation for the period?

Their common conditions are;
1. 11.2896 MHz synchronous master clock supplied to ES9018
2. I2S I/F
3. 44.1 kHz/16 bit PCM sources
4. OSF = ON, DPLL Bandwidth=No Bandwidth
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Old 7th April 2013, 09:41 AM   #2188
roender is offline roender  Romania
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Quote:
Originally Posted by Bunpei View Post
Totally three people in Japan tried the "No Bandwidth" experiments and all of them got the same longest periods, 96 seconds in spite that they applied such different I2S sources, SDTrans and QA-550.

Does anyone give a possible interpretation for the period?

Their common conditions are;
1. 11.2896 MHz synchronous master clock supplied to ES9018
2. I2S I/F
3. 44.1 kHz/16 bit PCM sources
4. OSF = ON, DPLL Bandwidth=No Bandwidth
Hi Bunpei,

How close to the DAC is the clock? In the particular case of SDtrans384, 11.2896Mhz is not a valid clock. So, how is MCLK supplied back to the transport?
In my case, I have two CCHD957 oscilators (45.1584MHz and 49.152MHz) located very close to the DAC and the MCLK for the transport is divided by a Potato Semi D flip-flop. The DPLL bandwidth is set to "Lowest" and there are no unlocks from 44.1/16 till 192/32 PCM nor for 64 or 128DSD.
I'm not sure if BIII DAC accepts "No Bandwidth" with standard firmware in order to make experiments but will be interesting to know how is works.
Please see the attached pictures of my setup.

Kind Regards,
Mihai
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Old 7th April 2013, 11:21 AM   #2189
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by roender View Post
... How close to the DAC is the clock? In the particular case of SDtrans384, 11.2896Mhz is not a valid clock. So, how is MCLK supplied back to the transport? ...
Among three, Tackbon uses SDTran384. Other two use QA-550 with NDK oscillator.
Tackbon's clock configuration is shown in his diagram.
Click the image to open in full size.

By the way, your implementation of Crystek oscillators is really admirable! You have also prepared your own AVCC power supplies for your BIII.
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Old 7th April 2013, 12:35 PM   #2190
AAK is offline AAK  United States
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Hi Bunpei,

Just a quick observation. On my setup with DPLL Bandwidth set to "No Bandwidth" using spdif inputs the ES9018 completely losses lock, but regains a very steady lock when the DPLL BW is multiplied by 128.

Best regards,

Al
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