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Old 4th March 2013, 03:24 PM   #2171
Zoran is offline Zoran  Serbia
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Quote:
Originally Posted by Tazmaniac View Post
Ok, go through old Dustin Forman post and you will get your answer.
But perhaps it did not know the ES9018 very well ....
Mono mode is just a shortcut to bypass your L+L/R+R or what ever you want I2S reformatting.
I dont't understand your interrogation about I2S clocking VS DAC conversion. The conversion is done on frame boundary. When the DAC look for L or R or L+R samples, sample are there with no time dependent ordering, it is the job of the I2S receiver stage.
it is simple
everything is the same like standsrd I2S
WS goes to change state one cycle prior to the MSB on every word start
SYS CLK is normal.
The content of the word L or R is the same...
everything is the same
Just order of the words are exchanged
Standard I2S have L following R word, and after that booth going to conversion
DAC does not mind what the content of the words or what word comes first or after that, Dac minds just that the bus following the protocol, and if it is in mutual synchronisation like it should be...
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Old 4th March 2013, 03:38 PM   #2172
Zoran is offline Zoran  Serbia
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Tazmaniac,
Dont get me wrong, but for the 5 time,
the issue is ES9008 NOT ES9018, please...
.
It is much easier, if You already know the answer,
to point me to via direct link or citation or just answer it...
...
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Old 4th March 2013, 07:58 PM   #2173
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Info given by Dustin to Russ White when the 9018 goes out:
Buffalo DAC (ESS Sabre 9008)
And don't get me wrong : all what I am saying is that native mono mode was a 9018 addition and does not exist on 9008 even if you could obtain the same result with external I2S pre-processing.
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Old 4th March 2013, 11:55 PM   #2174
Bunpei is offline Bunpei  Japan
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Default Effect of DPLL Bandwidth Parameter

I assume that the number of ES9018 based DAC users those who have tried a synchronous master clocking method is increasing. With the method we are almost free from the disastrous ES9018 specific "unlock" events even when we select "the lowest" bandwidth for 384kHz/32bit PCM I2S.

By the way, has anyone observed a DPLL bandwidth parameter dependence of variability of DPLL counter value under a constant synchronous master clocking condition?

The reason why I ask about it is that I have no good understanding on the role of "DPLL bandwidth" parameter.

Even under a synchronous master clocking scheme that Russ once described it somewhere as "DPLL is free-wheeling", there are slight value changes in a DPLL counter. Does the wider DPLL bandwidth parameter cause the larger fluctuation of DPLL counter value?

Last edited by Bunpei; 4th March 2013 at 11:59 PM.
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Old 6th March 2013, 01:28 PM   #2175
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Could you please point me how to accomplish the best solution of synchronous master clocking method with this dac (BIII)?
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Old 6th March 2013, 01:34 PM   #2176
roender is offline roender  Romania
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Quote:
Originally Posted by AndriyOL View Post
Could you please point me how to accomplish the best solution of synchronous master clocking method with this dac (BIII)?
Depends on your transport, especially if accepts external clock. What do you have as I2S source?
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Old 6th March 2013, 02:34 PM   #2177
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by roender View Post
Depends on your transport, especially if accepts external clock. What do you have as I2S source?
I agree with roender's view point.

There are three approaches on the allocation of master clock sources.

1. At a DAC side
acko's "Turbo Clock", Chiaki's sync-clock-DAC
Divided clock signals are sent back to a transport side.

2. At FIFO buffer inserted between a transport and a DAC
Ian's FIFO, FIFO designed by Mr. Kakuta of AIT LABO ( in Japan)

3. At a transport side
Chikai's SDTrans, Multiplier & jitter cleaner designed by Mr. Fujiwara (in Japan)
Multiplied clock signals are sent forward to a DAC side from a transport side.

In all the cases, you must prepare good clock generators.

Last edited by Bunpei; 6th March 2013 at 02:37 PM.
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Old 6th March 2013, 03:21 PM   #2178
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Quote:
Originally Posted by roender View Post
Depends on your transport, especially if accepts external clock. What do you have as I2S source?
PC sound card proccesor.

Quote:
Originally Posted by Bunpei View Post
There are three approaches on the allocation of master clock sources.
I consider waiting for multich 32bit USB-I2S DSD transport, in this regard I guess third approach will be better one?
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Last edited by AndriyOL; 6th March 2013 at 03:27 PM.
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Old 10th March 2013, 07:04 AM   #2179
Bunpei is offline Bunpei  Japan
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Default +1.2V power for ES9018

I'm sorry that I have not checked whether it is a FAQ or somewhere it is explained.

There are 7 power pins on ES9018 for +1.2V power;
1 VDD_L Analog Power(+1.2V) for Left channels
16 VDD_L Analog Power(+1.2V) for Left channels
20 VDD Digital Power(+1.2V) for core of chip
29 VDD Digital Power(+1.2V) for core of chip
33 VDD_R Analog Power(+1.2V) for Right channels
48 VDD_R Analog Power(+1.2V) for Right channels
61 VDD Digital Power(+1.2V) for core of chip

I understand that "Analog Power" means "related to analog DAC section" of the chip and "Digital Power" means "related to digital processing core section" and all power lines are connect to internal digital circuits.

Does any one have any clear empirical result that it's better for us to assign separate +1.2V regulators for "Analog Power" and "Digital Power" respectively?

I found acko's DAC board provides separate power input terminals.
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Old 10th March 2013, 10:35 AM   #2180
roender is offline roender  Romania
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This is an old post belonging to Russ White:

"All that the 1.2V supplies are used for (beside the core 1.2V) to drive the level shifters for the analog stage.

They do not need to be and there is no benefit from (in any measurable way according to Dustin) them having supplies that are separate from the core 1.2V supply.

Now some here may feel compelled to provide a separately regulated supply for the level shift drivers, but practically I can't find a good reason to do it. If Dustin says don't bother, I say I won't. So I didn't. I drive the level shifters from the same 1.2 volt regulator as the core uses."
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