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Old 7th February 2013, 07:21 PM   #2131
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Quote:
Originally Posted by Bunpei View Post
Oh, did you talk about register setting?
If so, the exact wording in datasheet is;

Register #17: Mode Control 5
[6] OSF_bypass
1'b1 => Send data directly from the I2S receiver to the IIR filter at 8x. This will cause the signal to bypass the FIR filters as well as the deemphasis filter, but will still apply the volume controls.
1'b0 => Use the OSF filter (normal operation)
Quote:
Originally Posted by glt View Post
Then you must be oversampling externally...
The 8x are for the "filter" to work..

Quote:
Originally Posted by RayCtech View Post
Hi Dustin

I have some questions I not have seen the answers for yet:

1. What are the minimum voltage levels the SPDIF input requires to work properly?

2. What are the DAC switching frequency - by that I mean switches the DAC output at 384k, 768k, 1536k or at some other frequecy?

What are the DAC switching frequency with these three conditions?
2.1. With 44.1k input and 40M clock?
2.2. With 44.1k input and 80M clock?
2.3. With 192k input and 80M clock?

3. Any register settings to change this??

Raymond
Quote:
Originally Posted by dusfor99 View Post
Hi Raymond,
1. The SPDIF input is just a CMOS input with shmidt trigger, so you really should use the comparator circuit to make the spdif input 0 to 3.3V

2. Switching frequency is XI/64. so
2.1 = 625kHz
2.2 = 1.25MHz
2.3 = 1.25MHz

3. No
I then understand that the oscillator used (22/24M, 40M, 45/49M, 80M, 90/98M or 100MHz) sets the REAL oversampling rate, and the DAC outputs are also switching at XI/64.

I also think that the oversampling will be at a integer rate with the proper oscillator frequencies and not integer when 40M, 80M or 100MHz oscillators are used.

I also use the SPDIF inputs with the OS filter disabled (for some years) even if this requires special programming / hardware setup.

Regarding the clock frequencies: A 22.5792MHZ oscillator works (very good fidelity) with 352.8k/32bit and 352.8k/24bit sources, also 24.576MHz works with 384k/32bit and 384k/24bit sources. Then the DAC outputs swings at 352.8k / 384k...

Last edited by RayCtech; 7th February 2013 at 07:49 PM.
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Old 7th February 2013, 11:00 PM   #2132
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Quote:
Originally Posted by RayCtech View Post
Custom built clocks (better than 1ps) -> clock distribution (adds 18fs jitter).
Clock distribution have OE (output enable) and can thus select 22/24M, 45/49M and 90/98M clocks. Distribution -> to each mono DAC, to potatosemi re-clocker and to ADC.

Always OS filter disabled for PCM.

Thus PCM plays just as good as DSD (DSD have no OS filter)
Thanks, that's what I was presuming, just confirming.

I am assuming the 22M clock is for ability to play double x DSD (requires >
3*FS) otherwise you could use an 11.xx / 12.xx Mhz and still get 352.8/384
PCM sans OSF. The 11.2896 / 12.288 will be potentially better again than 22
/ 24M clocks.

cheers
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Old 9th February 2013, 11:11 PM   #2133
Bunpei is offline Bunpei  Japan
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Does anyone succeed in establishing a stable play of DSD512 on the combination of ES9018 and Amanero COMBO384?
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Old 9th February 2013, 11:42 PM   #2134
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Quote:
Originally Posted by RayCtech View Post
...
2. What are the DAC switching frequency - by that I mean switches the DAC output at 384k, 768k, 1536k or at some other frequecy?
May I ask what "the DAC switching frequency" means?

In the original context, Raymond seemed to imagine the DAC as PWM or DSD ( 1 bit digital ) modulator and the term "switching" was likely to mean the similar one in a class-D amplifier.

Does it mean an output sampling frequency of 6-bit DAC segment?
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Old 11th February 2013, 10:01 PM   #2135
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Quote:
Originally Posted by Bunpei View Post
In the original context, Raymond seemed to imagine the DAC as PWM or DSD ( 1 bit digital ) modulator and the term "switching" was likely to mean the similar one in a class-D amplifier.
I was told you had issues with translation to and from Japanese some years ago.... It is a nuance when you are "lost in translation"
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Old 16th February 2013, 03:34 PM   #2136
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Anyway, I interpret the term "switching frequency" as a "a frequency domain notation of conversion interval of a '6 bit analog DAC' ( this term appears in "Technical Details of the Sabre Audio DAC"(the Sabre White Paper)".

When a master clock of ES9018 is 44.1kHz x 512= 22.5792 MHz, the switching frequency, XI/64, is 44.1kHz x 512 / 64 = 44.1kHz x 8 = 352.8 kHz.
When DXD ( 352.8 kHz /24 bit ) is played with "OSF_bypass", the sampling frequency of PCM is equal to the "switching frequency" of the 6 bit analog DAC that is designed for converting 6 bit delta-sigma modulated data.
On the other hand, in general, a delta-sigma modulated data is created by oversampling in such a far higher frequency as x 64 ( in the case of 1 bit delta-sigma modulation) of the original PCM fs.

I can't understand well such a case as shown above, "original PCM sampling frequency is equal to the sampling frequency of the internal 6 bit analog DAC in ES9018".
Is the original DXD data played in a degraded manner?

Last edited by Bunpei; 16th February 2013 at 03:37 PM.
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Old 16th February 2013, 04:17 PM   #2137
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Quote:
Originally Posted by Bunpei View Post
the 6 bit analog DAC that is designed for converting 6 bit delta-sigma modulated data.
Why would you want to use 6 bit ??

If I understand correctly: 6 bit is more or less equal to 64 digital levels in the analog conversion, but depending on pseudo / true mode and 2 ch / mono etc. this may differ...

Why not use 9 bit mode (mono DAC) and utilize all the possible 1024 digital levels in the analog conversion..

By using less than 9 bit mode in mono or 8 bit in 2 channel mode the noise may be lower as the DAC outputs (and other internal circuits) then can be paralleled, but the fidelity are better the more digital levels that are used...

As I see it the only cause to use 6 bit is to have 8 independent channels using one DAC chip..

Last edited by RayCtech; 16th February 2013 at 04:22 PM.
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Old 16th February 2013, 11:00 PM   #2138
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Quote:
Originally Posted by Bunpei View Post
I can't understand well such a case as shown above, "original PCM sampling frequency is equal to the sampling frequency of the internal 6 bit analog DAC in ES9018".
Is the original DXD data played in a degraded manner?
It is the similar situation to truncate 44.1kHz 24bit to 44.1kHz 16bit with noise shaping ,such as sony's SBM.
you can ensure sufficient SNR in low frequency band with shaping quantization noise distribution.
on the other hand,the resolution of higher frequency band will be degraded to less than its number of bit.
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Old 17th February 2013, 04:06 AM   #2139
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I think Raymond talked about "Quantizer bit depth" setting which is undocumented in their datasheet but well-known to "Sabrephiles".
Hifiduino Code and Buffalo III DAC H i F i D U I N O
ESS Sabre Reference DAC (8-channel)

The quantizer bit depth setting of larger than 6 employs combinations of multiple 6 bit analog DAC sections ( There are totally 16 analog DAC sections per one ES9018 chip) for one delta-sigma data longer than 6 bit.
As for 9 bit setting, one 9 bit number is broken into eight 6 bit numbers and the eight 6 bit numbers are routed to the eight analog sections. Eight output of those analog DAC sections should be merged into one wire outside the DAC chip. One must remember that the analog output is in not a "true differential mode" but in a "pseudo differential mode" on this 9 bit setting.

Anyway, even if we use the 9 bit quantizer bit length setting, an original 352.8 kHz/24 bit DXD PCM data is truncated into 352.8kHz/9 bit delta-sigma modulated data.

To Shinja
Thank you very much for letting me know Sony's "Super Bit Mapping" technology that was originally developed for converting 44.1kHz/20bit sources into 44.1kHz/16bit CD contents.
http://pdf.textfiles.com/manuals/STA...%20Mapping.pdf
In the article shown above, they say "by taking advantages of psychoacoutic principles".

To Raymond,
Your comment has made me realized why they offered the option of quantizer bit depth setting. Thank you very much for the comment.
By the way, how is the recent progress of your "8 channel DXD play using exaU2I" project?
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Old 17th February 2013, 08:30 AM   #2140
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Quote:
Originally Posted by Bunpei View Post
One must remember that the analog output is in not a "true differential mode" but in a "pseudo differential mode" on this 9 bit setting.
I expect your "quantizer references" are Dustin´s explanations (in this thread the 15th february 2008) for the ES9008 chip..

However - with the ES9018 chips I discovered and implemented the 9 bit "true differential mode"...
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