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Old 6th February 2013, 10:28 AM   #2101
Bunpei is offline Bunpei  Japan
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Join Date: Aug 2008
Most of Japanese ES9018 based DIY DAC users favor "the Lowest" setting of DPLL Bandwidth Parameter for I2S/DSD.
One of my friend says "No bandwidth" setting for DSD512 is the best though the play is not stable.
As for me, I like a DSD256 play of synchronous master clock of 90.3168 MHz/98.304 MHz the best within the range of my experiences. When I listened to a DSD256 sound for the first time, I felt a certain "breakthrough" and convinced a clear and great advantage of ES9018.

I'd like to recommend you learn how to set register values and make your explorations.
"glt" is kindly and generously offering both wonderful compilation of necessary information and his smart Arduino code for that purpose on his blog articles.
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Old 6th February 2013, 11:13 AM   #2102
Coris is offline Coris  Norway
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Hi Bunpei

As I wrote before about this subject (and repeat now), I made my experiments on an ESS9018 planted in Oppo player (BDP95). That because I have no answer to your question for now. I do not know how Oppo`s firmware has set up the DAC registry.
I will for sure repeat all those experiments on an Buffalo board, and I will for sure look at this aspect with the set up of the chip registries. It may happen in this year most likely. I will go deeper in those things, but for now I have some problems with the time...
But, I may repeat too, in that conditions Oppo have wrote the DAC firmware and set it up the registry, I have registered improvements using 125Mhz SAW oscillator.

Anyway, I just wonder why the DIY people who have already the experience and the adequate tools, do not try to understand why it may be improvements this way(s) of using this exceptional DAC chip. It will be a huge contribution for all of us, will save much time and work for they who may be new in this registry control of ESS9018.

You for example, could you help us very much if you will accept to solder an SAW in your system, or an 125Mhz one, read the registry , or set it up accordingly, try to see why it sounds better this way... and eventual come back here with your results/conclusions...
It couldn`t be nice?

Last edited by Coris; 6th February 2013 at 11:15 AM.
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Old 6th February 2013, 11:50 AM   #2103
Bunpei is offline Bunpei  Japan
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Hi, Coris,

As I wrote before about my thought, on my post in another thread,
ESS9018 - try new, try more...
ackoDAC based on ES9018
(and repeat now), I will not make my experiments other than a synchronous clocking.

I think it's better for you to make your experimental conditions clear at least before you present your subjective results on this thread.

Bunpei
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Old 6th February 2013, 03:38 PM   #2104
glt is offline glt  United States
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Join Date: Oct 2004
Quote:
Originally Posted by Bunpei View Post
Most of Japanese ES9018 based DIY DAC users favor "the Lowest" setting of DPLL Bandwidth Parameter for I2S/DSD.
One of my friend says "No bandwidth" setting for DSD512 is the best though the play is not stable.
As for me, I like a DSD256 play of synchronous master clock of 90.3168 MHz/98.304 MHz the best within the range of my experiences. When I listened to a DSD256 sound for the first time, I felt a certain "breakthrough" and convinced a clear and great advantage of ES9018.

I'd like to recommend you learn how to set register values and make your explorations.
"glt" is kindly and generously offering both wonderful compilation of necessary information and his smart Arduino code for that purpose on his blog articles.
"no bandwidth" in asynch is VERY stable: "no sound at all" :-)

I think Bunpei is on the right track, changing clock speed may affect other parameters such as the dpll settings, the quantization noise, filter performance, etc. With Arduino you could adjust those parameters and determine what is best...
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Last edited by glt; 6th February 2013 at 03:40 PM.
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Old 6th February 2013, 05:48 PM   #2105
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Quote:
Originally Posted by glt View Post
"no bandwidth" in asynch is VERY stable: "no sound at all" :-)

I think Bunpei is on the right track, changing clock speed may affect other parameters such as the dpll settings, the quantization noise, filter performance, etc. With Arduino you could adjust those parameters and determine what is best...
And also the clock speeds can be changed if you add clocks and control for that...

I run with clocks at 22/24M, 45/49M and 90/98M...
The fun of it is that the register settings that gives the best fidelity are identical for all clock speeds.
And even greater fun is it that it is the lowest clock speeds gives the best fidelity.

I have for sure tested clocks above 100MHz - and they was the identical 1ps jitter clocks that I have in the lower speeds.
I gave the overspeed clocks some days to settle before they was removed.
I cannot understand why the increased noise and reduced fidelity are preferred by some individuals, but it is for sure different...
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Old 7th February 2013, 01:18 AM   #2106
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Quote:
Originally Posted by Bunpei View Post
Most of Japanese ES9018 based DIY DAC users favor "the Lowest" setting of DPLL Bandwidth Parameter for I2S/DSD.
I find this to be the case in my experience as well. Using SDTrans and BIII with synchronous masterclock. However, I have not tried sampling rates higher than 24bit 196kHz and DSD256.
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Old 7th February 2013, 01:45 AM   #2107
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Is there an optimum fs ?
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Old 7th February 2013, 08:31 AM   #2108
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by KlipschKid View Post
Is there an optimum fs ?
I'm afraid your question is too simplified and non-definitive.
Within my limited experiences and based on my subjective criteria, the optimum fs are;
DSD: 11.2896 MHz
PCM: 352.8 kHz

On the other hand, sound quality of 44.1 kHz is also very high.
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Old 7th February 2013, 08:51 AM   #2109
PHEONIX is offline PHEONIX  Australia
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Quote:
Originally Posted by RayCtech View Post
And also the clock speeds can be changed if you add clocks and control for that...

I run with clocks at 22/24M, 45/49M and 90/98M...
The fun of it is that the register settings that gives the best fidelity are identical for all clock speeds.
And even greater fun is it that it is the lowest clock speeds gives the best fidelity.

I have for sure tested clocks above 100MHz - and they was the identical 1ps jitter clocks that I have in the lower speeds.
I gave the overspeed clocks some days to settle before they was removed.
I cannot understand why the increased noise and reduced fidelity are preferred by some individuals, but it is for sure different...


On the crystal front all things being equal , the lowest phase noise offset at say 10Hz (important metric for jitter performance) is always lower on crystal oscillators which are lower in frequency, phase noise increases with increasing oscillator frequency. Maybe this explains what your hearing .

Last edited by PHEONIX; 7th February 2013 at 08:55 AM.
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Old 7th February 2013, 09:02 AM   #2110
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Join Date: Aug 2007
Quote:
Originally Posted by Bunpei View Post
I'm afraid your question is too simplified and non-definitive.
Within my limited experiences and based on my subjective criteria, the optimum fs are;
DSD: 11.2896 MHz
PCM: 352.8 kHz

On the other hand, sound quality of 44.1 kHz is also very high.
I'm trying to make sense of the broadly different results - and I thought maybe somewhere between 512fs to 1024fs there is a sweet spot, so for 44.1Khz, we'd want a mclk between 22.5792Mhz and 45.1584Mhz. But maybe there is no sweet spot. Not that it matters - I prefer asynch with 50Mhz saw to synch with 45.1584Mhz Fox Xpresso, so that's what I'm gonna stick with.

Everybody gets to choose their own flavour. Raspberry ripple please !

Last edited by KlipschKid; 7th February 2013 at 09:06 AM.
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