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Old 1st February 2013, 10:53 PM   #2071
deanoUK is offline deanoUK  United Kingdom
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Quote:
Originally Posted by mjz3348 View Post
Can someone recommend a complete USB DAC using the ESS Sabre chip?
Plug and play.

Thanks
This is affordable.
iFi-audio iDAC
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Old 2nd February 2013, 01:33 AM   #2072
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by Bunpei View Post
 ...
My basic message is;
"ES9018 architecture has no mean to generate any shorter timing than one tick of master clock, for example 10ns for 100MHz MCLK. An asynchronous master clocking method brings the maximum 10ns quantum error along a time axis. On the other hand, a synchronous clocking can make the error to zero in theory."

If you think the message is incorrect, please post your idea with any certain supporting facts.
I got no counter comments on my speculation quoted above on this thread.
In a popular blog that one of regular members of this thread runns, a famous pioneering ES9018 based DAC kit designer showed his similar idea on this topic as his comments to a topic in the blog. (The designer might be the first person that recognized the advantage of synchronous master clocking as a designer outside ESS.)
A very active developer of FIFO buffers also expressed an similar understanding on his own thread of this forum.

Our speculation will give the following result by inference;
It must be useless to stick to jitters < 10ns on I2S/DSD input signals as long as you use asynchronous master clock of 100 MHz.

By the way, you may find some useful information in US Patent documents listed in the following page.
Dustin Forman - Canada | LinkedIn
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Old 2nd February 2013, 09:02 AM   #2073
Coris is offline Coris  Norway
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What about asynchronous master clock of 125 MHz (or max working)?

It still the same assertion valid: it must be useless to stick to jitters < 8ns on I2S/DSD input signals as long as you use asynchronous master clock of 125 MHz?
Is then better solution to use lower clock frequency, because better jitter tolerances (>10ns) for entire system?

As known, the higher the clock frequency, the lower its (induced) jitter errors for the same used working domain...

Last edited by Coris; 2nd February 2013 at 09:06 AM.
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Old 3rd February 2013, 01:20 PM   #2074
Shinja is offline Shinja  Japan
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Quote:
Originally Posted by roender View Post
Guys, would you please speculate about the ESS recommendation for inverted MCLK in sync mode?
IMHO, inverted MCLK is needed for taking into consideration the propagation delays at the I2S source if the clock is tightened to the DAC and remotely controls the source.
What are your opinions?
on the analogy of following posts, I think the reason is to avoid a meta stable when counting BCK(input clock) by MCLK(ref clock).

Quote:
Originally Posted by Bruno Putzeys View Post
@Arthur I think it would take us off topic to discuss in detail. ESS's claims regarding the SRC pertain to the actual interpolation process. They have done an absolutely splendid job there. The thing that causes problems is the ratio estimator (the bit that works out exactly what sampling time to interpolate). The bandwidth is too high which lets through time quantization errors. The circuit samples the incoming clock signal using its reference clock. This results in the addition of jitter with a peak-to-peak value of one reference clock period (e.g. 25ns for a 40MHz reference clock). Next the number of ref clock periods in one input clock cycle are counted and this constantly changing number is fed into a low-pass filter which outputs a cleaned-up version of the ratio between the reference and input clocks. This ratio is then used to space the "virtual resampling points" calculated by the interpolator. Of course the low pass filter doesn't output pure DC. The spectrum of the counter output consists of mix products between the two clocks. The filter can only attenuate those. The attenuated spectrum shows up as close-in FM sidebands exactly like jitter. DNR and THD measurements ignore those. The SRC successfully removes high-frequency jitter, thus guaranteeing good SNR, but it adds low-frequency phase modulation of the signal that wasn't even present in the input clock. All SRC's do this but the bandwidth of the low-pass filter determines whether this is an issue or not.

The attached two measurements were made on a standalone test chip for the ESS SRC which was never issued as a product, but the actual SRC did go on to be used in the Sabre DAC.
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Old 3rd February 2013, 04:01 PM   #2075
glt is offline glt  United States
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Hmmm...

Can it be argued then that the probability of getting those "peak jitter events" (10 ns) is greater in the synch mode than in the asynch mode? And that those peak jitter events cannot be filtered out?
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Old 3rd February 2013, 10:45 PM   #2076
Bunpei is offline Bunpei  Japan
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My interpretation is;

The "peak jitter events" is to be zero theoretically in the synch mode (synchronous master clocking).
That's the reason why the synchronous sounds better.
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Old 4th February 2013, 02:23 AM   #2077
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I'm quite surprised ESS haven't specified an optimum clock, or given data about the relationship between clock freq, jitter, sample rate, etc etc. I'd expect it in the datasheet, wouldn't you ? Has anyone done such tests and published the data ?

Four years on and people still can't download the barely adequate data sheet, and it seems quite a few things about this IC are still unknown; for example, jitter immunity, optimal clock speed for common sample rates, etc etc.

So how about asking ESS directly on behalf of the diy community ? I can't believe they would think it's in their interest to keep such information a secret.

Anyway, my point is, why guess when you can ask ?

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Old 4th February 2013, 07:09 AM   #2078
roender is offline roender  Romania
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Quote:
Originally Posted by Bunpei View Post
My interpretation is;

The "peak jitter events" is to be zero theoretically in the synch mode (synchronous master clocking).
That's the reason why the synchronous sounds better.
Even if jitter tolerance is around 10nS at the input of the DAC in asynchronous mode that doesn't mean that after the internal ASRC the I2S lines have jitter.
The problem here is the ASRC sound signature which becomes transparent in synchronous mode. In this mode the I2S input must be as jitter free as possible in order to have a good program fidelity.
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Old 4th February 2013, 07:49 AM   #2079
Coris is offline Coris  Norway
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Quote:
Originally Posted by KlipschKid View Post

So how about asking ESS directly on behalf of the diy community ? I can't believe they would think it's in their interest to keep such information a secret.

Anyway, my point is, why guess when you can ask ?

ESS Support Contact
Have you tried your self to ask something directly to ESS?

They never answer! That`s why some informations still be unknown... They are not friendly to give informations. There are only few people who were allowed or chosen by ESS to have some more informations than it is in that almost secret datasheet... And those informations have come out very selective...
There is a really strange behaviour of this company.
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Old 4th February 2013, 08:08 AM   #2080
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Quote:
Originally Posted by Coris View Post
Have you tried your self to ask something directly to ESS?

They never answer! That`s why some informations still be unknown... They are not friendly to give informations. There are only few people who were allowed or chosen by ESS to have some more informations than it is in that almost secret datasheet... And those informations have come out very selective...
There is a really strange behaviour of this company.
Hi,

I'll try and let you know.

Tom

Wow, that was fast. It won't even accept any of my work or private email addresses. ********* won't even take an enquiry. Anybody wanna buy my DAC ? Seriously. I'm not supporting crap companies like that.

Last edited by KlipschKid; 4th February 2013 at 08:16 AM.
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